return 0;
 }
 
+static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
+{
+       u32 fifo_outstanding_cmds, value;
+       int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
+
+       /* Check for fifo overflow during write */
+       ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
+       fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
+
+       if (fifo_outstanding_cmds) {
+               while (fifo_retry_count) {
+                       usleep_range(500, 510);
+                       ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
+                       fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
+                       fifo_retry_count--;
+                       if (fifo_outstanding_cmds == 0)
+                               return true;
+               }
+       } else {
+               return true;
+       }
+
+
+       return false;
+}
+
 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
                                     u8 dev_addr, u16 reg_addr)
 {
                usleep_range(150, 155);
 
        if (cmd_id == SWR_BROADCAST_CMD_ID) {
+               swrm_wait_for_wr_fifo_done(ctrl);
                /*
                 * sleep for 10ms for MSM soundwire variant to allow broadcast
                 * command to complete.
 {
        struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 
+       swrm_wait_for_wr_fifo_done(ctrl);
        sdw_release_stream(ctrl->sruntime[dai->id]);
        ctrl->sruntime[dai->id] = NULL;
        pm_runtime_mark_last_busy(ctrl->dev);
        struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
        int ret;
 
+       swrm_wait_for_wr_fifo_done(ctrl);
        if (!ctrl->clock_stop_not_supported) {
                /* Mask bus clash interrupt */
                ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;