drm/msm/dpu: move csc matrices to dpu_hw_util

Since the type and usage of CSC matrices is spanning across DPU
lets introduce a helper to the dpu_hw_util to return the CSC
corresponding to the request type. This will help to add more
supported CSC types such as the RGB to YUV one which is used in
the case of CDM.

changes in v3:
	- drop the extra wrapper and export the matrices directly

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/571816/
Link: https://lore.kernel.org/r/20231212205254.12422-5-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index fe083b2e5696ae4b133aa62ae9c474bc099b6f8c..aa50005042d16bf6681eac63417de1a609795b66 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -19,6 +19,36 @@
 #define MISR_CTRL_STATUS_CLEAR          BIT(10)
 #define MISR_CTRL_FREE_RUN_MASK         BIT(31)
 
+static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
+       {
+               /* S15.16 format */
+               0x00012A00, 0x00000000, 0x00019880,
+               0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+               0x00012A00, 0x00020480, 0x00000000,
+       },
+       /* signed bias */
+       { 0xfff0, 0xff80, 0xff80,},
+       { 0x0, 0x0, 0x0,},
+       /* unsigned clamp */
+       { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
+       { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
+};
+
+static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
+       {
+               /* S15.16 format */
+               0x00012A00, 0x00000000, 0x00019880,
+               0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+               0x00012A00, 0x00020480, 0x00000000,
+       },
+       /* signed bias */
+       { 0xffc0, 0xfe00, 0xfe00,},
+       { 0x0, 0x0, 0x0,},
+       /* unsigned clamp */
+       { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
+       { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
+};
+
 /*
  * This is the common struct maintained by each sub block
  * for mapping the register offsets in this block to the

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 3235ab13254004c4d01b6b5096ec2ce7f1df2f06..ff975ad51145658314abb3f1356e3fbfb11b91d2 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -21,6 +21,7 @@
 #include "dpu_kms.h"
 #include "dpu_formats.h"
 #include "dpu_hw_sspp.h"
+#include "dpu_hw_util.h"
 #include "dpu_trace.h"
 #include "dpu_crtc.h"
 #include "dpu_vbif.h"
@@ -508,36 +509,6 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
        }
 }
 
-static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
-       {
-               /* S15.16 format */
-               0x00012A00, 0x00000000, 0x00019880,
-               0x00012A00, 0xFFFF9B80, 0xFFFF3000,
-               0x00012A00, 0x00020480, 0x00000000,
-       },
-       /* signed bias */
-       { 0xfff0, 0xff80, 0xff80,},
-       { 0x0, 0x0, 0x0,},
-       /* unsigned clamp */
-       { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
-       { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
-};
-
-static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
-       {
-               /* S15.16 format */
-               0x00012A00, 0x00000000, 0x00019880,
-               0x00012A00, 0xFFFF9B80, 0xFFFF3000,
-               0x00012A00, 0x00020480, 0x00000000,
-               },
-       /* signed bias */
-       { 0xffc0, 0xfe00, 0xfe00,},
-       { 0x0, 0x0, 0x0,},
-       /* unsigned clamp */
-       { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
-       { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
-};
-
 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
                                                    const struct dpu_format *fmt)
 {