powerpc/perf: Update Power PMU cache_events to u64 type
authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Fri, 17 Jul 2020 14:38:15 +0000 (10:38 -0400)
committerMichael Ellerman <mpe@ellerman.id.au>
Wed, 22 Jul 2020 11:56:40 +0000 (21:56 +1000)
Events of type PERF_TYPE_HW_CACHE was described for Power PMU
as: int (*cache_events)[type][op][result];

where type, op, result values unpacked from the event attribute config
value is used to generate the raw event code at runtime.

So far the event code values which used to create these cache-related
events were within 32 bit and `int` type worked. In power10,
some of the event codes are of 64-bit value and hence update the
Power PMU cache_events to `u64` type in `power_pmu` struct.
Also propagate this change to existing all PMU driver code paths
which are using ppmu->cache_events.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-4-git-send-email-atrajeev@linux.vnet.ibm.com
arch/powerpc/include/asm/perf_event_server.h
arch/powerpc/perf/core-book3s.c
arch/powerpc/perf/generic-compat-pmu.c
arch/powerpc/perf/mpc7450-pmu.c
arch/powerpc/perf/power5+-pmu.c
arch/powerpc/perf/power5-pmu.c
arch/powerpc/perf/power6-pmu.c
arch/powerpc/perf/power7-pmu.c
arch/powerpc/perf/power8-pmu.c
arch/powerpc/perf/power9-pmu.c
arch/powerpc/perf/ppc970-pmu.c

index f9a36680339d1419900fc8ba395142eae516681c..14b8dc1305988284eee92d9d85dda55a9dcf2d91 100644 (file)
@@ -53,7 +53,7 @@ struct power_pmu {
        const struct attribute_group    **attr_groups;
        int             n_generic;
        int             *generic_events;
-       int             (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
+       u64             (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
                               [PERF_COUNT_HW_CACHE_OP_MAX]
                               [PERF_COUNT_HW_CACHE_RESULT_MAX];
 
index 18b1b6aae692f6a04ca73ed2c8514c38bfa6c78f..f4d07b5efd433a9d0192ae93f9584712079503d6 100644 (file)
@@ -1790,7 +1790,7 @@ static void hw_perf_event_destroy(struct perf_event *event)
 static int hw_perf_cache_event(u64 config, u64 *eventp)
 {
        unsigned long type, op, result;
-       int ev;
+       u64 ev;
 
        if (!ppmu->cache_events)
                return -EINVAL;
index 5e5a54d5588e9ee14f7bb6792a4606a3196be35c..eb8a6aaf4cc14b3420a7537aa3cafa3b9f4fed19 100644 (file)
@@ -101,7 +101,7 @@ static int compat_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [ C(L1D) ] = {
                [ C(OP_READ) ] = {
                        [ C(RESULT_ACCESS) ] = 0,
index 826de253aa4dc8f7e3666910cfb095d5469aa0e8..1919e9df9165abfccc9ea38835b6605e47a8a302 100644 (file)
@@ -361,7 +361,7 @@ static int mpc7450_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0,              0x225   },
                [C(OP_WRITE)] = {       0,              0x227   },
index 5f0821e54f04250b4b45d852060e154dedef78c6..a62b2cd7914fd92ee376b78fc4293023d497fdd7 100644 (file)
@@ -619,7 +619,7 @@ static int power5p_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x1c10a8,       0x3c1088        },
                [C(OP_WRITE)] = {       0x2c10a8,       0xc10c3         },
index 426021d4b44c33c595704035d7e9e55bb97c5889..8732b587cf71d17848d2e3cecc8890c14f46035f 100644 (file)
@@ -561,7 +561,7 @@ static int power5_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x4c1090,       0x3c1088        },
                [C(OP_WRITE)] = {       0x3c1090,       0xc10c3         },
index e343a51a989eb1375f9e5dc5f95a09fbf8609eb0..0e318cf87129daa15a4f578bf6718bac9813d806 100644 (file)
@@ -481,7 +481,7 @@ static int power6_generic_events[] = {
  * are event codes.
  * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
  */
-static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x280030,       0x80080         },
                [C(OP_WRITE)] = {       0x180032,       0x80088         },
index 315233691314afae41777483ed0575926e10952e..5e0bf09cf077d109a290031ea03e38ffeb5bed1b 100644 (file)
@@ -333,7 +333,7 @@ static int power7_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0xc880,         0x400f0 },
                [C(OP_WRITE)] = {       0,              0x300f0 },
index 3a5fcc20ff31695e86ac292c3d622dab70519b57..5282e8415ddfeffa97df74b3929f18ba88bc2aa4 100644 (file)
@@ -253,7 +253,7 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [ C(L1D) ] = {
                [ C(OP_READ) ] = {
                        [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
index 08c3ef7961982606a38d8e9508784c625e4df720..05dae38b969a5fef609d83c91d23a84040dc3439 100644 (file)
@@ -310,7 +310,7 @@ static void power9_config_bhrb(u64 pmu_bhrb_filter)
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [ C(L1D) ] = {
                [ C(OP_READ) ] = {
                        [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
index 89a90ab6a6c87ccadadf7a2f6a600bc673f181a5..d35223fb112c064722a3d861757482bb362eff82 100644 (file)
@@ -432,7 +432,7 @@ static int ppc970_generic_events[] = {
  * 0 means not supported, -1 means nonsensical, other values
  * are event codes.
  */
-static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x8810,         0x3810  },
                [C(OP_WRITE)] = {       0x7810,         0x813   },