return ret;
 }
 
-static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
+void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 {
        struct dwc3_ep          *dep;
 
        __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 }
 
-static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
+void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
 {
        struct dwc3_gadget_ep_cmd_params params;
        u32                     cmd;
        int                     ret;
 
-       if (!dep->resource_index)
+       /*
+        * For status/DATA OUT stage, TRB will be queued on ep0 out
+        * endpoint for which resource index is zero. Hence allow
+        * queuing ENDXFER command for ep0 out endpoint.
+        */
+       if (!dep->resource_index && dep->number)
                return;
 
        cmd = DWC3_DEPCMD_ENDTRANSFER;
 
                reg |= DWC3_DALEPENA_EP(dep->number);
                dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 
+               dep->trb_dequeue = 0;
+               dep->trb_enqueue = 0;
+
                if (usb_endpoint_xfer_control(desc))
                        goto out;
 
                /* Initialize the TRB ring */
-               dep->trb_dequeue = 0;
-               dep->trb_enqueue = 0;
                memset(dep->trb_pool, 0,
                       sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 
 
        /* begin to receive SETUP packets */
        dwc->ep0state = EP0_SETUP_PHASE;
+       dwc->ep0_bounced = false;
        dwc->link_state = DWC3_LINK_STATE_SS_DIS;
        dwc->delayed_status = false;
        dwc3_ep0_out_start(dwc);
        }
 
        dwc3_reset_gadget(dwc);
+
+       /*
+        * From SNPS databook section 8.1.2, the EP0 should be in setup
+        * phase. So ensure that EP0 is in setup phase by issuing a stall
+        * and restart if EP0 is not in setup phase.
+        */
+       if (dwc->ep0state != EP0_SETUP_PHASE) {
+               unsigned int    dir;
+
+               dir = !!dwc->ep0_expect_in;
+               if (dwc->ep0state == EP0_DATA_PHASE)
+                       dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
+               else
+                       dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
+
+               dwc->eps[0]->trb_enqueue = 0;
+               dwc->eps[1]->trb_enqueue = 0;
+
+               dwc3_ep0_stall_and_restart(dwc);
+       }
+
        /*
         * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
         * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
 
 void dwc3_ep0_interrupt(struct dwc3 *dwc,
                const struct dwc3_event_depevt *event);
 void dwc3_ep0_out_start(struct dwc3 *dwc);
+void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
+void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,