return 0;
 }
 
+static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf)
+{
+       struct spi_transfer xfers[2] = {
+               {
+                       .tx_buf = &priv->tx,
+                       .len = 1,
+               }, {
+                       .tx_buf = buf,
+                       .len = MPF_SPI_FRAME_SIZE,
+               },
+       };
+       int ret;
+
+       ret = mpf_poll_status(priv, 0);
+       if (ret < 0)
+               return ret;
+
+       priv->tx = MPF_SPI_FRAME;
+
+       return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
+}
+
 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
 {
-       struct spi_transfer xfers[2] = { 0 };
        struct mpf_priv *priv = mgr->priv;
        struct device *dev = &mgr->dev;
        int ret, i;
                return -EINVAL;
        }
 
-       xfers[0].tx_buf = &priv->tx;
-       xfers[0].len = 1;
-
        for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
-               xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
-               xfers[1].len = MPF_SPI_FRAME_SIZE;
-
-               ret = mpf_poll_status(priv, 0);
-               if (ret >= 0) {
-                       priv->tx = MPF_SPI_FRAME;
-                       ret = spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
-               }
-
+               ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE);
                if (ret) {
                        dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
                                i, count / MPF_SPI_FRAME_SIZE);