drm/msm/dpu: Add DSC configuration for SM8150 and SM8250

These DSC blocks on CTL V1 need to set its corresponding PINGPONG block
index in a hardware register to configure where to send pixel output to,
via the newly-added DPU_DSC_OUTPUT_CTRL feature flag.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/515689/
Link: https://lore.kernel.org/r/20221221231943.1961117-9-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index dc206f54e7b5a7c84a88ba5a15da348d1e983d27..0f3da480b0660a624aa3f498ad1b4ff862bd080a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1811,18 +1811,25 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
 /*************************************************************
  * DSC sub blocks config
  *************************************************************/
-#define DSC_BLK(_name, _id, _base) \
+#define DSC_BLK(_name, _id, _base, _features) \
        {\
        .name = _name, .id = _id, \
        .base = _base, .len = 0x140, \
-       .features = 0, \
+       .features = _features, \
        }
 
 static struct dpu_dsc_cfg sdm845_dsc[] = {
-       DSC_BLK("dsc_0", DSC_0, 0x80000),
-       DSC_BLK("dsc_1", DSC_1, 0x80400),
-       DSC_BLK("dsc_2", DSC_2, 0x80800),
-       DSC_BLK("dsc_3", DSC_3, 0x80c00),
+       DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
+       DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
+       DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
+       DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
+};
+
+static struct dpu_dsc_cfg sm8150_dsc[] = {
+       DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+       DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
+       DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
+       DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
 };
 
 /*************************************************************
@@ -2610,6 +2617,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
        .mixer = sm8150_lm,
        .dspp_count = ARRAY_SIZE(sm8150_dspp),
        .dspp = sm8150_dspp,
+       .dsc_count = ARRAY_SIZE(sm8150_dsc),
+       .dsc = sm8150_dsc,
        .pingpong_count = ARRAY_SIZE(sm8150_pp),
        .pingpong = sm8150_pp,
        .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
@@ -2684,6 +2693,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
        .mixer = sm8150_lm,
        .dspp_count = ARRAY_SIZE(sm8150_dspp),
        .dspp = sm8150_dspp,
+       .dsc_count = ARRAY_SIZE(sm8150_dsc),
+       .dsc = sm8150_dsc,
        .pingpong_count = ARRAY_SIZE(sm8150_pp),
        .pingpong = sm8150_pp,
        .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),