clk: qcom: cpu-8996: change setup sequence to follow vendor kernel

Add missing register writes to CPU clocks setup procedure. This makes it
follow the setup procedure used in msm-3.18 kernel.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-14-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index bd4d3370eb9748bf6e8d07deb750bb41af3d1a0f..ba9b7c3f8d3e384fc56876bae2c7f24a972a7bbb 100644 (file)
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -76,10 +76,16 @@ enum _pmux_input {
 #define PWRCL_REG_OFFSET 0x0
 #define PERFCL_REG_OFFSET 0x80000
 #define MUX_OFFSET     0x40
+#define CLK_CTL_OFFSET 0x44
+#define CLK_CTL_AUTO_CLK_SEL BIT(8)
 #define ALT_PLL_OFFSET 0x100
 #define SSSCTL_OFFSET 0x160
+#define PSCTL_OFFSET 0x164
 
 #define PMUX_MASK      0x3
+#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
+#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
+       FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
 
 static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
        [PLL_OFF_L_VAL] = 0x04,
@@ -439,6 +445,14 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
        /* Ensure write goes through before PLLs are reconfigured */
        udelay(5);
 
+       /* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
+       regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET,
+                          MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
+                          MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
+       regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET,
+                          MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
+                          MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
+
        clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
        clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
        clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
@@ -447,11 +461,24 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
        /* Wait for PLL(s) to lock */
        udelay(50);
 
+       /* Enable auto clock selection for both clusters */
+       regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET,
+                          CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
+       regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET,
+                          CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
+
+       /* Ensure write goes through before muxes are switched */
+       udelay(5);
+
        qcom_cpu_clk_msm8996_acd_init(regmap);
 
+       /* Pulse swallower and soft-start settings */
+       regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
+       regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
+
        /* Switch clusters to use the ACD leg */
-       regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2);
-       regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2);
+       regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32);
+       regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32);
 
        for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {
                ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);