clk: qcom: Merge alt alpha plls for qcm2260, sm6115

The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and
BRAMMO alpha pll offsets. Move these common offsets to the shared place
to avoid duplication. The new layouts have a suffix EVO similar to LUCID
and RIVIAN.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 9cc38234d45d64effcf8cc896c3816d1b3e92d16..34bb93b66357963ccede159d917707bcd96a27a4 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -166,6 +166,27 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                [PLL_OFF_TEST_CTL] = 0x28,
                [PLL_OFF_TEST_CTL_U] = 0x2c,
        },
+       [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] =  {
+               [PLL_OFF_L_VAL] = 0x04,
+               [PLL_OFF_ALPHA_VAL] = 0x08,
+               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+               [PLL_OFF_TEST_CTL] = 0x10,
+               [PLL_OFF_TEST_CTL_U] = 0x14,
+               [PLL_OFF_USER_CTL] = 0x18,
+               [PLL_OFF_USER_CTL_U] = 0x1c,
+               [PLL_OFF_CONFIG_CTL] = 0x20,
+               [PLL_OFF_STATUS] = 0x24,
+       },
+       [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] =  {
+               [PLL_OFF_L_VAL] = 0x04,
+               [PLL_OFF_ALPHA_VAL] = 0x08,
+               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+               [PLL_OFF_TEST_CTL] = 0x10,
+               [PLL_OFF_TEST_CTL_U] = 0x14,
+               [PLL_OFF_USER_CTL] = 0x18,
+               [PLL_OFF_CONFIG_CTL] = 0x1C,
+               [PLL_OFF_STATUS] = 0x20,
+       },
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index ea90a61bf774925c55f3aca7dd054046a5a13858..08bfda1fe6a6ba8dd5035d3a74b08f7c153cfdc6 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -19,6 +19,8 @@ enum {
        CLK_ALPHA_PLL_TYPE_ZONDA,
        CLK_ALPHA_PLL_TYPE_LUCID_EVO,
        CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
+       CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
+       CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
        CLK_ALPHA_PLL_TYPE_MAX,
 };
 

diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
index b6fa7b8e80066cc64f1609f77ac8d2629202e738..7792b8f237047bedb4fbdd53d025ab3251c310ff 100644 (file)
--- a/drivers/clk/qcom/gcc-qcm2290.c
+++ b/drivers/clk/qcom/gcc-qcm2290.c
@@ -54,33 +54,9 @@ static const struct pll_vco spark_vco[] = {
        { 750000000, 1500000000, 1 },
 };
 
-static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
-       [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
-               [PLL_OFF_L_VAL] = 0x04,
-               [PLL_OFF_ALPHA_VAL] = 0x08,
-               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
-               [PLL_OFF_TEST_CTL] = 0x10,
-               [PLL_OFF_TEST_CTL_U] = 0x14,
-               [PLL_OFF_USER_CTL] = 0x18,
-               [PLL_OFF_USER_CTL_U] = 0x1C,
-               [PLL_OFF_CONFIG_CTL] = 0x20,
-               [PLL_OFF_STATUS] = 0x24,
-       },
-       [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
-               [PLL_OFF_L_VAL] = 0x04,
-               [PLL_OFF_ALPHA_VAL] = 0x08,
-               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
-               [PLL_OFF_TEST_CTL] = 0x10,
-               [PLL_OFF_TEST_CTL_U] = 0x14,
-               [PLL_OFF_USER_CTL] = 0x18,
-               [PLL_OFF_CONFIG_CTL] = 0x1C,
-               [PLL_OFF_STATUS] = 0x20,
-       },
-};
-
 static struct clk_alpha_pll gpll0 = {
        .offset = 0x0,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(0),
@@ -106,7 +82,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
        .post_div_table = post_div_table_gpll0_out_aux2,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll0_out_aux2",
                .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -117,7 +93,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
 
 static struct clk_alpha_pll gpll1 = {
        .offset = 0x1000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(1),
@@ -147,7 +123,7 @@ static struct clk_alpha_pll gpll10 = {
        .offset = 0xa000,
        .vco_table = spark_vco,
        .num_vco = ARRAY_SIZE(spark_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(10),
@@ -179,7 +155,7 @@ static struct clk_alpha_pll gpll11 = {
        .offset = 0xb000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .flags = SUPPORTS_DYNAMIC_UPDATE,
        .clkr = {
                .enable_reg = 0x79000,
@@ -197,7 +173,7 @@ static struct clk_alpha_pll gpll11 = {
 
 static struct clk_alpha_pll gpll3 = {
        .offset = 0x3000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(3),
@@ -223,7 +199,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
        .post_div_table = post_div_table_gpll3_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll3_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
@@ -234,7 +210,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
 
 static struct clk_alpha_pll gpll4 = {
        .offset = 0x4000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(4),
@@ -251,7 +227,7 @@ static struct clk_alpha_pll gpll4 = {
 
 static struct clk_alpha_pll gpll5 = {
        .offset = 0x5000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(5),
@@ -268,7 +244,7 @@ static struct clk_alpha_pll gpll5 = {
 
 static struct clk_alpha_pll gpll6 = {
        .offset = 0x6000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(6),
@@ -294,7 +270,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
        .post_div_table = post_div_table_gpll6_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll6_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@@ -305,7 +281,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
 
 static struct clk_alpha_pll gpll7 = {
        .offset = 0x7000,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(7),
@@ -340,7 +316,7 @@ static struct clk_alpha_pll gpll8 = {
        .offset = 0x8000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .flags = SUPPORTS_DYNAMIC_UPDATE,
        .clkr = {
                .enable_reg = 0x79000,
@@ -367,7 +343,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
        .post_div_table = post_div_table_gpll8_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll8_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@@ -393,7 +369,7 @@ static struct clk_alpha_pll gpll9 = {
        .offset = 0x9000,
        .vco_table = brammo_vco,
        .num_vco = ARRAY_SIZE(brammo_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(9),
@@ -419,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
        .post_div_table = post_div_table_gpll9_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
        .width = 2,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll9_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },

diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index dc2a99c3bc06549767a4158c0cc5a359942d3bb5..565f9912039fe4fdb9f91b654766bfdf5b8c9471 100644 (file)
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -53,35 +53,11 @@ static struct pll_vco gpll10_vco[] = {
        { 750000000, 1500000000, 1 },
 };
 
-static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
-       [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
-               [PLL_OFF_L_VAL] = 0x04,
-               [PLL_OFF_ALPHA_VAL] = 0x08,
-               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
-               [PLL_OFF_TEST_CTL] = 0x10,
-               [PLL_OFF_TEST_CTL_U] = 0x14,
-               [PLL_OFF_USER_CTL] = 0x18,
-               [PLL_OFF_USER_CTL_U] = 0x1c,
-               [PLL_OFF_CONFIG_CTL] = 0x20,
-               [PLL_OFF_STATUS] = 0x24,
-       },
-       [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
-               [PLL_OFF_L_VAL] = 0x04,
-               [PLL_OFF_ALPHA_VAL] = 0x08,
-               [PLL_OFF_ALPHA_VAL_U] = 0x0c,
-               [PLL_OFF_TEST_CTL] = 0x10,
-               [PLL_OFF_TEST_CTL_U] = 0x14,
-               [PLL_OFF_USER_CTL] = 0x18,
-               [PLL_OFF_CONFIG_CTL] = 0x1C,
-               [PLL_OFF_STATUS] = 0x20,
-       },
-};
-
 static struct clk_alpha_pll gpll0 = {
        .offset = 0x0,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(0),
@@ -107,7 +83,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
        .post_div_table = post_div_table_gpll0_out_aux2,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll0_out_aux2",
                .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -127,7 +103,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_main = {
        .post_div_table = post_div_table_gpll0_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll0_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -149,7 +125,7 @@ static struct clk_alpha_pll gpll10 = {
        .offset = 0xa000,
        .vco_table = gpll10_vco,
        .num_vco = ARRAY_SIZE(gpll10_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(10),
@@ -175,7 +151,7 @@ static struct clk_alpha_pll_postdiv gpll10_out_main = {
        .post_div_table = post_div_table_gpll10_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll10_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
@@ -201,7 +177,7 @@ static struct clk_alpha_pll gpll11 = {
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
        .flags = SUPPORTS_DYNAMIC_UPDATE,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(11),
@@ -227,7 +203,7 @@ static struct clk_alpha_pll_postdiv gpll11_out_main = {
        .post_div_table = post_div_table_gpll11_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll11_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
@@ -241,7 +217,7 @@ static struct clk_alpha_pll gpll3 = {
        .offset = 0x3000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(3),
@@ -260,7 +236,7 @@ static struct clk_alpha_pll gpll4 = {
        .offset = 0x4000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(4),
@@ -286,7 +262,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_main = {
        .post_div_table = post_div_table_gpll4_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll4_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
@@ -299,7 +275,7 @@ static struct clk_alpha_pll gpll6 = {
        .offset = 0x6000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(6),
@@ -325,7 +301,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
        .post_div_table = post_div_table_gpll6_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll6_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@@ -338,7 +314,7 @@ static struct clk_alpha_pll gpll7 = {
        .offset = 0x7000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(7),
@@ -364,7 +340,7 @@ static struct clk_alpha_pll_postdiv gpll7_out_main = {
        .post_div_table = post_div_table_gpll7_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll7_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
@@ -392,7 +368,7 @@ static struct clk_alpha_pll gpll8 = {
        .offset = 0x8000,
        .vco_table = default_vco,
        .num_vco = ARRAY_SIZE(default_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .flags = SUPPORTS_DYNAMIC_UPDATE,
        .clkr = {
                .enable_reg = 0x79000,
@@ -419,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
        .post_div_table = post_div_table_gpll8_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
        .width = 4,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll8_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@@ -443,7 +419,7 @@ static struct clk_alpha_pll gpll9 = {
        .offset = 0x9000,
        .vco_table = gpll9_vco,
        .num_vco = ARRAY_SIZE(gpll9_vco),
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
        .clkr = {
                .enable_reg = 0x79000,
                .enable_mask = BIT(9),
@@ -469,7 +445,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
        .post_div_table = post_div_table_gpll9_out_main,
        .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
        .width = 2,
-       .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll9_out_main",
                .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },