if (phy_type == TYPE_DP)
return cdns_torrent_dp_init(phy);
+ /**
+ * Spread spectrum generation is not required or supported
+ * for SGMII/QSGMII
+ */
+ if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
+ ssc = NO_SSC;
+
/* PHY configuration specific registers for single link */
link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
if (link_cmn_vals) {
.num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
};
+/* Single SGMII/QSGMII link configuration */
+static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
+ {0x0000, PHY_PLL_CFG},
+ {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
+};
+
+static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
+ {0x0000, XCVR_DIAG_HSCLK_SEL},
+ {0x0003, XCVR_DIAG_HSCLK_DIV},
+ {0x0013, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
+ .reg_pairs = sl_sgmii_link_cmn_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
+ .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
+};
+
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
{0x0004, CMN_PLL0_DSM_DIAG_M0},
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,