drm/amd/display: Change to IMMEDIATE mode from FRAME mode

[Why]
Change in DCN10 to use IMMEDIATE_UPDATE mode for AFMT is not
reflected in DCN30 as it uses VPG.

[How]
Use IMMEDIATE_UPDATE mode for DCN30 in VPG.

Signed-off-by: Judy Cai <HuiYi.Cai@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
index 9c0020c8a73084dc7b4ac38f0138223142e6c475..8cfd181b4d5f7f866b5a672c6543026b0b6bc104 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
@@ -103,69 +103,69 @@ static void vpg3_update_generic_info_packet(
                }
        }
 
-       /* atomically update double-buffered GENERIC0 registers in frame mode
+       /* atomically update double-buffered GENERIC0 registers in immediate mode
         * (update at next block_update when block_update_lock == 0).
         */
        switch (packet_index) {
        case 0:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC0_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC0_IMMEDIATE_UPDATE, 1);
                break;
        case 1:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC1_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC1_IMMEDIATE_UPDATE, 1);
                break;
        case 2:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC2_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC2_IMMEDIATE_UPDATE, 1);
                break;
        case 3:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC3_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC3_IMMEDIATE_UPDATE, 1);
                break;
        case 4:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC4_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC4_IMMEDIATE_UPDATE, 1);
                break;
        case 5:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC5_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC5_IMMEDIATE_UPDATE, 1);
                break;
        case 6:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC6_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC6_IMMEDIATE_UPDATE, 1);
                break;
        case 7:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC7_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC7_IMMEDIATE_UPDATE, 1);
                break;
        case 8:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC8_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC8_IMMEDIATE_UPDATE, 1);
                break;
        case 9:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC9_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC9_IMMEDIATE_UPDATE, 1);
                break;
        case 10:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC10_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC10_IMMEDIATE_UPDATE, 1);
                break;
        case 11:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC11_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC11_IMMEDIATE_UPDATE, 1);
                break;
        case 12:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC12_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC12_IMMEDIATE_UPDATE, 1);
                break;
        case 13:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC13_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC13_IMMEDIATE_UPDATE, 1);
                break;
        case 14:
-               REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
-                               VPG_GENERIC14_FRAME_UPDATE, 1);
+               REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
+                               VPG_GENERIC14_IMMEDIATE_UPDATE, 1);
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
index 0284092630f15b72dc6c5db513c050672b2a54a0..6161e9e6635560fa0d76f9912a9f8393aec09f5d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
@@ -34,13 +34,15 @@
        SRI(VPG_GENERIC_STATUS, VPG, id), \
        SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
        SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
-       SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id)
+       SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
+       SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id)
 
 struct dcn30_vpg_registers {
        uint32_t VPG_GENERIC_STATUS;
        uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;
        uint32_t VPG_GENERIC_PACKET_DATA;
        uint32_t VPG_GSP_FRAME_UPDATE_CTRL;
+       uint32_t VPG_GSP_IMMEDIATE_UPDATE_CTRL;
 };
 
 #define DCN3_VPG_MASK_SH_LIST(mask_sh)\
@@ -65,7 +67,22 @@ struct dcn30_vpg_registers {
        SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC11_FRAME_UPDATE, mask_sh),\
        SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC12_FRAME_UPDATE, mask_sh),\
        SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC13_FRAME_UPDATE, mask_sh),\
-       SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC14_FRAME_UPDATE, mask_sh)
+       SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC14_FRAME_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC8_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC9_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC10_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC11_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC12_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC13_IMMEDIATE_UPDATE, mask_sh),\
+       SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC14_IMMEDIATE_UPDATE, mask_sh)
 
 #define VPG_DCN3_REG_FIELD_LIST(type) \
        type VPG_GENERIC_CONFLICT_OCCURED;\
@@ -89,7 +106,22 @@ struct dcn30_vpg_registers {
        type VPG_GENERIC11_FRAME_UPDATE;\
        type VPG_GENERIC12_FRAME_UPDATE;\
        type VPG_GENERIC13_FRAME_UPDATE;\
-       type VPG_GENERIC14_FRAME_UPDATE
+       type VPG_GENERIC14_FRAME_UPDATE;\
+       type VPG_GENERIC0_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC1_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC2_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC3_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC4_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC5_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC6_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC7_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC8_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC9_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC10_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC11_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC12_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC13_IMMEDIATE_UPDATE;\
+       type VPG_GENERIC14_IMMEDIATE_UPDATE
 
 
 struct dcn30_vpg_shift {