arm64/kprobe: Optimize the performance of patching single-step slot

Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.

Since I and D caches are coherent within single-step slot from
aarch64_insn_patch_text_nosync(), hence no need to do it again via
flush_icache_range().

Acked-by: Will Deacon <will@kernel.org>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
Link: https://lore.kernel.org/r/20220927022435.129965-4-liaochang1@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index d1d1823202453d2259536636099b75b7d0f09d99..c9e4d072028561d8b0730a8da68f193ad14197ee 100644 (file)
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -44,13 +44,28 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
 static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
 {
        kprobe_opcode_t *addr = p->ainsn.api.insn;
-       void *addrs[] = {addr, addr + 1};
-       u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
 
-       /* prepare insn slot */
-       aarch64_insn_patch_text(addrs, insns, 2);
-
-       flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
+       /*
+        * Prepare insn slot, Mark Rutland points out it depends on a coupe of
+        * subtleties:
+        *
+        * - That the I-cache maintenance for these instructions is complete
+        *   *before* the kprobe BRK is written (and aarch64_insn_patch_text_nosync()
+        *   ensures this, but just omits causing a Context-Synchronization-Event
+        *   on all CPUS).
+        *
+        * - That the kprobe BRK results in an exception (and consequently a
+        *   Context-Synchronoization-Event), which ensures that the CPU will
+        *   fetch thesingle-step slot instructions *after* this, ensuring that
+        *   the new instructions are used
+        *
+        * It supposes to place ISB after patching to guarantee I-cache maintenance
+        * is observed on all CPUS, however, single-step slot is installed in
+        * the BRK exception handler, so it is unnecessary to generate
+        * Contex-Synchronization-Event via ISB again.
+        */
+       aarch64_insn_patch_text_nosync(addr, p->opcode);
+       aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
 
        /*
         * Needs restoring of return address after stepping xol.