kselftest/arm64: Extend vector configuration API tests to cover SME
authorMark Brown <broonie@kernel.org>
Tue, 19 Apr 2022 11:22:39 +0000 (12:22 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Thu, 28 Apr 2022 16:57:11 +0000 (17:57 +0100)
Provide RDVL helpers for SME and extend the main vector configuration tests
to cover SME.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419112247.711548-32-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
tools/testing/selftests/arm64/fp/.gitignore
tools/testing/selftests/arm64/fp/Makefile
tools/testing/selftests/arm64/fp/rdvl-sme.c [new file with mode: 0644]
tools/testing/selftests/arm64/fp/rdvl.S
tools/testing/selftests/arm64/fp/rdvl.h
tools/testing/selftests/arm64/fp/vec-syscfg.c

index c50d86331ed2fbec7c0e9259d32a938e7e01df7b..6e9a610c5e5d10a2bf8fc14b2dd0fe4f0ca465cd 100644 (file)
@@ -1,5 +1,6 @@
 fp-pidbench
 fpsimd-test
+rdvl-sme
 rdvl-sve
 sve-probe-vls
 sve-ptrace
index 95f0b877a060ba01db39165e659047a7429d8a0b..a224fff8082bfa835aac48da1d71118f5bdc432c 100644 (file)
@@ -3,7 +3,7 @@
 CFLAGS += -I../../../../../usr/include/
 TEST_GEN_PROGS := sve-ptrace sve-probe-vls vec-syscfg
 TEST_PROGS_EXTENDED := fp-pidbench fpsimd-test fpsimd-stress \
-       rdvl-sve \
+       rdvl-sme rdvl-sve \
        sve-test sve-stress \
        vlset
 
@@ -13,6 +13,7 @@ fp-pidbench: fp-pidbench.S asm-utils.o
        $(CC) -nostdlib $^ -o $@
 fpsimd-test: fpsimd-test.o asm-utils.o
        $(CC) -nostdlib $^ -o $@
+rdvl-sme: rdvl-sme.o rdvl.o
 rdvl-sve: rdvl-sve.o rdvl.o
 sve-ptrace: sve-ptrace.o
 sve-probe-vls: sve-probe-vls.o rdvl.o
diff --git a/tools/testing/selftests/arm64/fp/rdvl-sme.c b/tools/testing/selftests/arm64/fp/rdvl-sme.c
new file mode 100644 (file)
index 0000000..49b0b2e
--- /dev/null
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <stdio.h>
+
+#include "rdvl.h"
+
+int main(void)
+{
+       int vl = rdvl_sme();
+
+       printf("%d\n", vl);
+
+       return 0;
+}
index c916c1c9defdc877946f3ae405a0e19f5d821a81..20dc29996dc69e962e6f1fde7b4098eeb94ccce3 100644 (file)
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // Copyright (C) 2021 ARM Limited.
 
+#include "sme-inst.h"
+
 .arch_extension sve
 
 .globl rdvl_sve
@@ -8,3 +10,11 @@ rdvl_sve:
        hint    34                      // BTI C
        rdvl    x0, #1
        ret
+
+.globl rdvl_sme
+rdvl_sme:
+       hint    34                      // BTI C
+
+       rdsvl   0, 1
+
+       ret
index 7c9d953fc9e7337e5794196af9574265797cd2fd..5d323679fbc940bf1325197cacf49e8e96f2d0c3 100644 (file)
@@ -3,6 +3,7 @@
 #ifndef RDVL_H
 #define RDVL_H
 
+int rdvl_sme(void);
 int rdvl_sve(void);
 
 #endif
index c90658811a83857ffcdd0c32c6a4062cff9b22bc..9bcfcdc34ee9475c1b9720dcb7faebe997cb57b7 100644 (file)
@@ -51,6 +51,16 @@ static struct vec_data vec_data[] = {
                .prctl_set = PR_SVE_SET_VL,
                .default_vl_file = "/proc/sys/abi/sve_default_vector_length",
        },
+       {
+               .name = "SME",
+               .hwcap_type = AT_HWCAP2,
+               .hwcap = HWCAP2_SME,
+               .rdvl = rdvl_sme,
+               .rdvl_binary = "./rdvl-sme",
+               .prctl_get = PR_SME_GET_VL,
+               .prctl_set = PR_SME_SET_VL,
+               .default_vl_file = "/proc/sys/abi/sme_default_vector_length",
+       },
 };
 
 static int stdio_read_integer(FILE *f, const char *what, int *val)