crypto: hisilicon/qm - add comments and remove redundant array element

1. Remove redundant array element, prevent the size obtained by
ARRAY_SIZE() from qm_log_hw_error is greater than actual size.
2. Add comments in function qm_set_vf_mse() and qm_cq_ctx_cfg()
to make it easier to understand.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 7d22412774baaac7a322362403e3d70a843a56dd..7ed079a9c9291db9e082e2fbf7083ad5774d1b58 100644 (file)
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -391,7 +391,6 @@ static const struct hisi_qm_hw_error qm_hw_error[] = {
        { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
        { .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },
        { .int_msk = BIT(14), .msg = "qm_flr_timeout" },
-       { /* sentinel */ }
 };
 
 static const char * const qm_db_timeout[] = {
@@ -1889,6 +1888,11 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
                cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth));
                cqc.w8 = 0; /* rand_qc */
        }
+       /*
+        * Enable request finishing interrupts defaultly.
+        * So, there will be some interrupts until disabling
+        * this.
+        */
        cqc.dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
        cqc.base_l = cpu_to_le32(lower_32_bits(qp->cqe_dma));
        cqc.base_h = cpu_to_le32(upper_32_bits(qp->cqe_dma));
@@ -3879,6 +3883,11 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
        int pos;
        int i;
 
+       /*
+        * Since function qm_set_vf_mse is called only after SRIOV is enabled,
+        * pci_find_ext_capability cannot return 0, pos does not need to be
+        * checked.
+        */
        pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
        pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
        if (set)