writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
-               &ch->ch_neo_uart->fctr);
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
+              &ch->ch_neo_uart->fctr);
 
        /* Feed the UART our trigger levels */
        writeb(8, &ch->ch_neo_uart->tfifo);
        /* Turn on UART enhanced bits */
        writeb(efr, &ch->ch_neo_uart->efr);
 
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
-               &ch->ch_neo_uart->fctr);
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
+              &ch->ch_neo_uart->fctr);
        ch->ch_r_watermark = 4;
 
        writeb(32, &ch->ch_neo_uart->rfifo);
        /* Turn on UART enhanced bits */
        writeb(efr, &ch->ch_neo_uart->efr);
 
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
               &ch->ch_neo_uart->fctr);
        ch->ch_r_watermark = 4;
 
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
-               &ch->ch_neo_uart->fctr);
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
+              &ch->ch_neo_uart->fctr);
 
        writeb(8, &ch->ch_neo_uart->tfifo);
        ch->ch_t_tlevel = 8;
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
-               &ch->ch_neo_uart->fctr);
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
+              &ch->ch_neo_uart->fctr);
 
        ch->ch_r_watermark = 0;
 
        writeb(efr, &ch->ch_neo_uart->efr);
 
        /* Turn on table D, with 8 char hi/low watermarks */
-       writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
-               &ch->ch_neo_uart->fctr);
+       writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
+              &ch->ch_neo_uart->fctr);
 
        ch->ch_r_watermark = 0;
 
        if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
                return;
 
-       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR),
+       writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
               &ch->ch_neo_uart->isr_fcr);
        neo_pci_posting_flush(ch->ch_bd);
 
 
        /* Clear out UART and FIFO */
        readb(&ch->ch_neo_uart->txrx);
-       writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
+       writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
               &ch->ch_neo_uart->isr_fcr);
        readb(&ch->ch_neo_uart->lsr);
        readb(&ch->ch_neo_uart->msr);