drm/amdgpu: add gmc support for dimgrey_cavefish

Same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index bde63e7cd5015ac8c70eb21a0967fdccd06b8192..d535dfa84bdf9fee7b3b108bc8b4db6306a444c1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -763,6 +763,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
                case CHIP_SIENNA_CICHLID:
                case CHIP_NAVY_FLOUNDER:
                case CHIP_VANGOGH:
+               case CHIP_DIMGREY_CAVEFISH:
                default:
                        adev->gmc.gart_size = 512ULL << 20;
                        break;
@@ -829,6 +830,7 @@ static int gmc_v10_0_sw_init(void *handle)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
        case CHIP_VANGOGH:
+       case CHIP_DIMGREY_CAVEFISH:
                adev->num_vmhubs = 2;
                /*
                 * To fulfill 4-level page support,
@@ -943,6 +945,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
        case CHIP_VANGOGH:
+       case CHIP_DIMGREY_CAVEFISH:
                break;
        default:
                break;