drm/amdgpu/vcn:Move SPG mode mc resume after MPC control

Move Static Power Gate mode mc resume after MPC control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 29f711b57506309917a8cfd0ed3b84348e2d99c9..3275eaff6fba80fb595fb678137ce6cd80aa3346 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -780,8 +780,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
        /* disable clock gating */
        vcn_v1_0_disable_clock_gating(adev);
 
-       vcn_v1_0_mc_resume_spg_mode(adev);
-
        /* disable interupt */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
                        ~UVD_MASTINT_EN__VCPU_EN_MASK);
@@ -840,6 +838,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
                (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
                (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 
+       vcn_v1_0_mc_resume_spg_mode(adev);
+
        /* take all subblocks out of reset, except VCPU */
        WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);