coresight-tpdm: Add CMB dataset support

CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit
can be enabled for data collection by writing 1 to the first bit of
CMB_CR register. This change is to add enable/disable function for
CMB dataset by writing CMB_CR register.

Reviewed-by: James Clark <james.clark@arm.com>
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1707024641-22460-5-git-send-email-quic_taozha@quicinc.com

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index 4b1296d11360b9f87e94891e95393209a35b8d5f..1bb1d8e83501a3e0c8c1522a0a69b261b65a267b 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -263,6 +263,19 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
        writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
 }
 
+static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)
+{
+       u32 val;
+
+       if (!tpdm_has_cmb_dataset(drvdata))
+               return;
+
+       val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
+       /* Set the enable bit of CMB control register to 1 */
+       val |= TPDM_CMB_CR_ENA;
+       writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
+
 /*
  * TPDM enable operations
  * The TPDM or Monitor serves as data collection component for various
@@ -276,6 +289,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)
        CS_UNLOCK(drvdata->base);
 
        tpdm_enable_dsb(drvdata);
+       tpdm_enable_cmb(drvdata);
 
        CS_LOCK(drvdata->base);
 }
@@ -312,12 +326,26 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
        writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
 }
 
+static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata)
+{
+       u32 val;
+
+       if (!tpdm_has_cmb_dataset(drvdata))
+               return;
+
+       val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
+       /* Set the enable bit of CMB control register to 0 */
+       val &= ~TPDM_CMB_CR_ENA;
+       writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
+
 /* TPDM disable operations */
 static void __tpdm_disable(struct tpdm_drvdata *drvdata)
 {
        CS_UNLOCK(drvdata->base);
 
        tpdm_disable_dsb(drvdata);
+       tpdm_disable_cmb(drvdata);
 
        CS_LOCK(drvdata->base);
 }

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index ddaf333fa1c250bff3acc450394cf70b5b35f70d..a442d9c6e4ac4864c30cf442bec280ad839c4cc2 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -9,6 +9,12 @@
 /* The max number of the datasets that TPDM supports */
 #define TPDM_DATASETS       7
 
+/* CMB Subunit Registers */
+#define TPDM_CMB_CR            (0xA00)
+
+/* Enable bit for CMB subunit */
+#define TPDM_CMB_CR_ENA                BIT(0)
+
 /* DSB Subunit Registers */
 #define TPDM_DSB_CR            (0x780)
 #define TPDM_DSB_TIER          (0x784)
@@ -79,10 +85,12 @@
  *
  * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
  * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
+ * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0
  */
 
 #define TPDM_PIDR0_DS_IMPDEF   BIT(0)
 #define TPDM_PIDR0_DS_DSB      BIT(1)
+#define TPDM_PIDR0_DS_CMB      BIT(2)
 
 #define TPDM_DSB_MAX_LINES     256
 /* MAX number of EDCR registers */
@@ -224,4 +232,9 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)
 {
        return (drvdata->datasets & TPDM_PIDR0_DS_DSB);
 }
+
+static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata)
+{
+       return (drvdata->datasets & TPDM_PIDR0_DS_CMB);
+}
 #endif  /* _CORESIGHT_CORESIGHT_TPDM_H */