byVT3253B0_AGC4_RFMD2959[ii][0],
                                        byVT3253B0_AGC4_RFMD2959[ii][1]);
 
-                       VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
+                       iowrite32(0x23, iobase + MAC_REG_ITRTMSET);
                        MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
                }
                priv->abyBBVGA[0] = 0x18;
 
                qwTSFOffset = CARDqGetTSFOffset(byRxRate, qwBSSTimestamp,
                                                local_tsf);
                /* adjust TSF, HW's TSF add TSF Offset reg */
-               VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST,
-                            (u32)qwTSFOffset);
-               VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST + 4,
-                            (u32)(qwTSFOffset >> 32));
+               iowrite32((u32)qwTSFOffset, priv->port_offset + MAC_REG_TSFOFST);
+               iowrite32((u32)(qwTSFOffset >> 32), priv->port_offset + MAC_REG_TSFOFST + 4);
                MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL,
                              TFTCTL_TSFSYNCEN);
        }
        iowrite16(wBeaconInterval, priv->port_offset + MAC_REG_BI);
        priv->wBeaconInterval = wBeaconInterval;
        /* Set NextTBTT */
-       VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);
-       VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT + 4,
-                    (u32)(qwNextTBTT >> 32));
+       iowrite32((u32)qwNextTBTT, priv->port_offset + MAC_REG_NEXTTBTT);
+       iowrite32((u32)(qwNextTBTT >> 32), priv->port_offset + MAC_REG_NEXTTBTT + 4);
        MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
 
        return true;
        MACvSetCurrTXDescAddr(TYPE_AC0DMA, priv, priv->td1_pool_dma);
 
        /* set MAC Beacon TX pointer */
-       VNSvOutPortD(priv->port_offset + MAC_REG_BCNDMAPTR, priv->tx_beacon_dma);
+       iowrite32((u32)priv->tx_beacon_dma, priv->port_offset + MAC_REG_BCNDMAPTR);
 }
 
 /*
        }
 
        /* set perPkt mode */
-       VNSvOutPortD(priv->port_offset + MAC_REG_RXDMACTL0, RX_PERPKT);
-       VNSvOutPortD(priv->port_offset + MAC_REG_RXDMACTL1, RX_PERPKT);
+       iowrite32(RX_PERPKT, priv->port_offset + MAC_REG_RXDMACTL0);
+       iowrite32(RX_PERPKT, priv->port_offset + MAC_REG_RXDMACTL1);
        /* set MAC RD pointer */
        MACvSetCurrRx0DescAddr(priv, priv->rd0_pool_dma);
 
         /* swap over to get correct write order */
        swap(phy.swap[0], phy.swap[1]);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_1, phy.field_write);
+       iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_1);
 
        /* RSPINF_b_2 */
        vnt_get_phy_field(priv, 14,
 
        swap(phy.swap[0], phy.swap[1]);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_2, phy.field_write);
+       iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_2);
 
        /* RSPINF_b_5 */
        vnt_get_phy_field(priv, 14,
 
        swap(phy.swap[0], phy.swap[1]);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_5, phy.field_write);
+       iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_5);
 
        /* RSPINF_b_11 */
        vnt_get_phy_field(priv, 14,
 
        swap(phy.swap[0], phy.swap[1]);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_11, phy.field_write);
+       iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_11);
 
        /* RSPINF_a_6 */
        s_vCalculateOFDMRParameter(RATE_6M,
 
        qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval);
        /* Set NextTBTT */
-       VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);
-       VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32));
+       iowrite32((u32)qwNextTBTT, iobase + MAC_REG_NEXTTBTT);
+       iowrite32((u32)(qwNextTBTT >> 32), iobase + MAC_REG_NEXTTBTT + 4);
        MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
 }
 
 
        qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval);
        /* Set NextTBTT */
-       VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwTSF);
-       VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32));
+       iowrite32((u32)qwTSF, iobase + MAC_REG_NEXTTBTT);
+       iowrite32((u32)(qwTSF >> 32), iobase + MAC_REG_NEXTTBTT + 4);
        MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
        pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF);
 }
 
         * update ISR counter
         */
        while (isr && priv->vif) {
-               VNSvOutPortD(priv->port_offset + MAC_REG_ISR, isr);
+               iowrite32(isr, priv->port_offset + MAC_REG_ISR);
 
                if (isr & ISR_FETALERR) {
                        pr_debug(" ISR_FETALERR\n");
        if (priv->vif)
                vnt_interrupt_process(priv);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_IMR, IMR_MASK_VALUE);
+       iowrite32(IMR_MASK_VALUE, priv->port_offset + MAC_REG_IMR);
 }
 
 static irqreturn_t vnt_interrupt(int irq,  void *arg)
 
        schedule_work(&priv->interrupt_work);
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_IMR, 0);
+       iowrite32(0, priv->port_offset + MAC_REG_IMR);
 
        return IRQ_HANDLED;
 }
        device_init_registers(priv);
 
        dev_dbg(&priv->pcid->dev, "enable MAC interrupt\n");
-       VNSvOutPortD(priv->port_offset + MAC_REG_IMR, IMR_MASK_VALUE);
+       iowrite32(IMR_MASK_VALUE, priv->port_offset + MAC_REG_IMR);
 
        ieee80211_wake_queues(hw);
 
                        if (priv->mc_list_count > 2) {
                                MACvSelectPage1(priv->port_offset);
 
-                               VNSvOutPortD(priv->port_offset +
-                                            MAC_REG_MAR0, 0xffffffff);
-                               VNSvOutPortD(priv->port_offset +
-                                           MAC_REG_MAR0 + 4, 0xffffffff);
+                               iowrite32(0xffffffff, priv->port_offset + MAC_REG_MAR0);
+                               iowrite32(0xffffffff, priv->port_offset + MAC_REG_MAR0 + 4);
 
                                MACvSelectPage0(priv->port_offset);
                        } else {
                                MACvSelectPage1(priv->port_offset);
 
-                               VNSvOutPortD(priv->port_offset +
-                                            MAC_REG_MAR0, (u32)multicast);
-                               VNSvOutPortD(priv->port_offset +
-                                            MAC_REG_MAR0 + 4,
-                                            (u32)(multicast >> 32));
+                               iowrite32((u32)multicast, priv->port_offset +  MAC_REG_MAR0);
+                               iowrite32((u32)(multicast >> 32),
+                                         priv->port_offset + MAC_REG_MAR0 + 4);
 
                                MACvSelectPage0(priv->port_offset);
                        }
 
 {
        void __iomem *io_base = priv->port_offset;
        /* disable MAC IMR */
-       VNSvOutPortD(io_base + MAC_REG_IMR, 0);
+       iowrite32(0, io_base + MAC_REG_IMR);
        MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
        /* stop the adapter */
        if (!MACbSafeStop(priv)) {
 
        unsigned long dwData;                                           \
        dwData = ioread32(iobase + MAC_REG_RXDMACTL0);                  \
        if (dwData & DMACTL_RUN)                                        \
-               VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
+               iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL0);     \
        else                                                            \
-               VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
+               iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL0);      \
 } while (0)
 
 #define MACvReceive1(iobase)                                           \
        unsigned long dwData;                                           \
        dwData = ioread32(iobase + MAC_REG_RXDMACTL1);                  \
        if (dwData & DMACTL_RUN)                                        \
-               VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
+               iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL1);     \
        else                                                            \
-               VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
+               iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL1);      \
 } while (0)
 
 #define MACvTransmit0(iobase)                                          \
        unsigned long dwData;                                           \
        dwData = ioread32(iobase + MAC_REG_TXDMACTL0);                  \
        if (dwData & DMACTL_RUN)                                        \
-               VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
+               iowrite32(DMACTL_WAKE, iobase + MAC_REG_TXDMACTL0);     \
        else                                                            \
-               VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
+               iowrite32(DMACTL_RUN, iobase + MAC_REG_TXDMACTL0);      \
 } while (0)
 
 #define MACvTransmitAC0(iobase)                                        \
        unsigned long dwData;                                           \
        dwData = ioread32(iobase + MAC_REG_AC0DMACTL);                  \
        if (dwData & DMACTL_RUN)                                        \
-               VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
+               iowrite32(DMACTL_WAKE, iobase + MAC_REG_AC0DMACTL);     \
        else                                                            \
-               VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
+               iowrite32(DMACTL_RUN, iobase + MAC_REG_AC0DMACTL);      \
 } while (0)
 
 #define MACvClearStckDS(iobase)                                        \
        unsigned long dwOrgValue;                                       \
        dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);                  \
        dwOrgValue = dwOrgValue | ENCFG_PROTECTMD;                      \
-       VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
+       iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);             \
 } while (0)
 
 #define MACvDisableProtectMD(iobase)                                   \
        unsigned long dwOrgValue;                                       \
        dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);                  \
        dwOrgValue = dwOrgValue & ~ENCFG_PROTECTMD;                     \
-       VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
+       iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);             \
 } while (0)
 
 #define MACvEnableBarkerPreambleMd(iobase)                             \
        unsigned long dwOrgValue;                                       \
        dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);                  \
        dwOrgValue = dwOrgValue | ENCFG_BARKERPREAM;                    \
-       VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
+       iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);             \
 } while (0)
 
 #define MACvDisableBarkerPreambleMd(iobase)                            \
        unsigned long dwOrgValue;                                       \
        dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);                  \
        dwOrgValue = dwOrgValue & ~ENCFG_BARKERPREAM;                   \
-       VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
+       iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);             \
 } while (0)
 
 #define MACvSetBBType(iobase, byTyp)                                   \
        dwOrgValue = ioread32(iobase + MAC_REG_ENCFG);                  \
        dwOrgValue = dwOrgValue & ~ENCFG_BBTYPE_MASK;                   \
        dwOrgValue = dwOrgValue | (unsigned long)byTyp;                 \
-       VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
+       iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG);             \
 } while (0)
 
 #define MACvSetRFLE_LatchBase(iobase)                                 \
 
        unsigned short ww;
        unsigned long dwValue;
 
-       VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);
+       iowrite32((u32)dwData, iobase + MAC_REG_IFREGCTL);
 
        /* W_MAX_TIMEOUT is the timeout period */
        for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 
 
        priv->wBCNBufLen = sizeof(*short_head) + skb->len;
 
-       VNSvOutPortD(priv->port_offset + MAC_REG_BCNDMAPTR, priv->tx_beacon_dma);
+       iowrite32((u32)priv->tx_beacon_dma, priv->port_offset + MAC_REG_BCNDMAPTR);
 
        iowrite16(priv->wBCNBufLen, priv->port_offset + MAC_REG_BCNDMACTL + 2);
        /* Set auto Transmit on */
 
 
 /* For memory mapped IO */
 
-#define VNSvOutPortD(dwIOAddress, dwData) \
-       iowrite32((u32)(dwData), dwIOAddress)
-
 /*---------------------  Export Classes  ----------------------------*/
 
 /*---------------------  Export Variables  --------------------------*/