arm64: dts: sc7180: Add qspi opps and power-domains

Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sc7180

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 2be81a2a1512ab004549ae1f92eec85e979e9d2a..34a6d833f014c3bfc2ca50b5a0809df7f2706082 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2407,6 +2407,25 @@
                        status = "disabled";
                };
 
+               qspi_opp_table: qspi-opp-table {
+                       compatible = "operating-points-v2";
+
+                       opp-75000000 {
+                               opp-hz = /bits/ 64 <75000000>;
+                               required-opps = <&rpmhpd_opp_low_svs>;
+                       };
+
+                       opp-150000000 {
+                               opp-hz = /bits/ 64 <150000000>;
+                               required-opps = <&rpmhpd_opp_svs>;
+                       };
+
+                       opp-300000000 {
+                               opp-hz = /bits/ 64 <300000000>;
+                               required-opps = <&rpmhpd_opp_nom>;
+                       };
+               };
+
                qspi: spi@88dc000 {
                        compatible = "qcom,qspi-v1";
                        reg = <0 0x088dc000 0 0x600>;
@@ -2419,6 +2438,8 @@
                        interconnects = <&gem_noc MASTER_APPSS_PROC
                                        &config_noc SLAVE_QSPI_0>;
                        interconnect-names = "qspi-config";
+                       power-domains = <&rpmhpd SC7180_CX>;
+                       operating-points-v2 = <&qspi_opp_table>;
                        status = "disabled";
                };