drm/amdgpu: support IMU front door load
authorLikun Gao <Likun.Gao@amd.com>
Tue, 5 Apr 2022 17:42:51 +0000 (13:42 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:43:53 +0000 (10:43 -0400)
Support for front door to load IMU firmware.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

index dfb778cd2f82f8a513c6942086bdb64f4e041466..ac8a2876dfd4ddaa30b30677bff7f7019f850e20 100644 (file)
@@ -2205,6 +2205,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
                *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
                break;
+       case AMDGPU_UCODE_ID_IMU_I:
+               *type = GFX_FW_TYPE_IMU_I;
+               break;
+       case AMDGPU_UCODE_ID_IMU_D:
+               *type = GFX_FW_TYPE_IMU_D;
+               break;
        case AMDGPU_UCODE_ID_MAXIMUM:
        default:
                return -EINVAL;
index adf17bdddb65c0a5e8ccca27adf7da1ef2e2b5e3..9c99d62e51d4565b44790eadcd10445ad23f8ecb 100644 (file)
@@ -649,6 +649,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
        const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
        const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
+       const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
        u8 *ucode_addr;
 
        if (NULL == ucode->fw)
@@ -666,6 +667,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
        mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
        sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
+       imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
 
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
                switch (ucode->ucode_id) {
@@ -762,6 +764,17 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                        ucode->ucode_size = ucode->fw->size;
                        ucode_addr = (u8 *)ucode->fw->data;
                        break;
+               case AMDGPU_UCODE_ID_IMU_I:
+                       ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
+                       break;
+               case AMDGPU_UCODE_ID_IMU_D:
+                       ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
+                               le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
+                       break;
                default:
                        ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
                        ucode_addr = (u8 *)ucode->fw->data +
index c6417778510c01355c4a64097497d561e52a08db..127c034202a9195c735d5cadf73ae51dc2b729a2 100644 (file)
@@ -397,6 +397,8 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_CP_MES_DATA,
        AMDGPU_UCODE_ID_CP_MES1,
        AMDGPU_UCODE_ID_CP_MES1_DATA,
+       AMDGPU_UCODE_ID_IMU_I,
+       AMDGPU_UCODE_ID_IMU_D,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,