arm64: dts: microchip: sparx5: correct CPU address-cells

There is no reason for CPU node #address-cells to be set at 2, so lets
change them to 1 and update the reg property accordingly.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index ed6f57ce38f7fc11b8e184c6c6c8cbe24f03efb8..4996499cc738f69e2f29c19609fd5582c74d2f8e 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -24,7 +24,7 @@
        };
 
        cpus {
-               #address-cells = <2>;
+               #address-cells = <1>;
                #size-cells = <0>;
                cpu-map {
                        cluster0 {
@@ -39,14 +39,14 @@
                cpu0: cpu@0 {
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
-                       reg = <0x0 0x0>;
+                       reg = <0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
                };
                cpu1: cpu@1 {
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
-                       reg = <0x0 0x1>;
+                       reg = <0x1>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
                };