drm/msm/dpu: fix maxlinewidth for writeback block

Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.

This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.

Fix the maxlinewidth for writeback block on sm8250.

changes in v3:
	- correct the Fixes tag

Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/489887/
Link: https://lore.kernel.org/r/1655406084-17407-2-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index de4291936cb221c15ee99b12714bd72cbdb89be4..c7d46cd8c35e1e84cd2a2c2ae4a6a9eb740f583d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1288,7 +1288,7 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
  * Writeback blocks config
  *************************************************************/
 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
-               __xin_id, vbif_id, _reg, _wb_done_bit) \
+               __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
        { \
        .name = _name, .id = _id, \
        .base = _base, .len = 0x2c8, \
@@ -1298,13 +1298,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
        .clk_ctrl = _clk_ctrl, \
        .xin_id = __xin_id, \
        .vbif_idx = vbif_id, \
-       .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \
+       .maxlinewidth = _max_linewidth, \
        .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
        }
 
 static const struct dpu_wb_cfg sm8250_wb[] = {
        WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
-                       VBIF_RT, MDP_SSPP_TOP0_INTR, 4),
+                       VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
 };
 
 /*************************************************************