riscv: dts: renesas: r9a07g043f: Add L2 cache node

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403255a854061b66efa235e70b0f164..c8d63a8f7d8662eab4979526cac697c2fc866e5f 100644 (file)
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@
                        i-cache-line-size = <0x40>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <0x40>;
+                       next-level-cache = <&l2cache>;
                        clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
                        operating-points-v2 = <&cluster0_opp>;
 
@@ -56,4 +57,15 @@
                resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
                interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
        };
+
+       l2cache: cache-controller@13400000 {
+               compatible = "andestech,ax45mp-cache", "cache";
+               reg = <0x0 0x13400000 0x0 0x100000>;
+               interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+               cache-size = <0x40000>;
+               cache-line-size = <64>;
+               cache-sets = <1024>;
+               cache-unified;
+               cache-level = <2>;
+       };
 };