riscv: Rename Kconfig.erratas to Kconfig.errata

Errata is already plural for erratum. Rename it to make the
grammar gooder.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230224154601.88163-3-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 04898c50ef1d9e40e62db4158294157bf723586b..ab78f677f1878025972ab0cb890e5d17fa98585d 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -245,7 +245,7 @@ config AS_HAS_INSN
        def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
 
 source "arch/riscv/Kconfig.socs"
-source "arch/riscv/Kconfig.erratas"
+source "arch/riscv/Kconfig.errata"
 
 menu "Platform type"
 

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
new file mode 100644 (file)
index 0000000..69621ae
--- /dev/null
+++ b/arch/riscv/Kconfig.errata
@@ -0,0 +1,82 @@
+menu "CPU errata selection"
+
+config ERRATA_SIFIVE
+       bool "SiFive errata"
+       depends on !XIP_KERNEL
+       select RISCV_ALTERNATIVE
+       help
+         All SiFive errata Kconfig depend on this Kconfig. Disabling
+         this Kconfig will disable all SiFive errata. Please say "Y"
+         here if your platform uses SiFive CPU cores.
+
+         Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_SIFIVE_CIP_453
+       bool "Apply SiFive errata CIP-453"
+       depends on ERRATA_SIFIVE && 64BIT
+       default y
+       help
+         This will apply the SiFive CIP-453 errata to add sign extension
+         to the $badaddr when exception type is instruction page fault
+         and instruction access fault.
+
+         If you don't know what to do here, say "Y".
+
+config ERRATA_SIFIVE_CIP_1200
+       bool "Apply SiFive errata CIP-1200"
+       depends on ERRATA_SIFIVE && 64BIT
+       default y
+       help
+         This will apply the SiFive CIP-1200 errata to repalce all
+         "sfence.vma addr" with "sfence.vma" to ensure that the addr
+         has been flushed from TLB.
+
+         If you don't know what to do here, say "Y".
+
+config ERRATA_THEAD
+       bool "T-HEAD errata"
+       depends on !XIP_KERNEL
+       select RISCV_ALTERNATIVE
+       help
+         All T-HEAD errata Kconfig depend on this Kconfig. Disabling
+         this Kconfig will disable all T-HEAD errata. Please say "Y"
+         here if your platform uses T-HEAD CPU cores.
+
+         Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_THEAD_PBMT
+       bool "Apply T-Head memory type errata"
+       depends on ERRATA_THEAD && 64BIT && MMU
+       select RISCV_ALTERNATIVE_EARLY
+       default y
+       help
+         This will apply the memory type errata to handle the non-standard
+         memory type bits in page-table-entries on T-Head SoCs.
+
+         If you don't know what to do here, say "Y".
+
+config ERRATA_THEAD_CMO
+       bool "Apply T-Head cache management errata"
+       depends on ERRATA_THEAD && MMU
+       select RISCV_DMA_NONCOHERENT
+       default y
+       help
+         This will apply the cache management errata to handle the
+         non-standard handling on non-coherent operations on T-Head SoCs.
+
+         If you don't know what to do here, say "Y".
+
+config ERRATA_THEAD_PMU
+       bool "Apply T-Head PMU errata"
+       depends on ERRATA_THEAD && RISCV_PMU_SBI
+       default y
+       help
+         The T-Head C9xx cores implement a PMU overflow extension very
+         similar to the core SSCOFPMF extension.
+
+         This will apply the overflow errata to handle the non-standard
+         behaviour via the regular SBI PMU driver and interface.
+
+         If you don't know what to do here, say "Y".
+
+endmenu # "CPU errata selection"

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
deleted file mode 100644 (file)
index 69621ae..0000000
--- a/arch/riscv/Kconfig.erratas
+++ /dev/null
@@ -1,82 +0,0 @@
-menu "CPU errata selection"
-
-config ERRATA_SIFIVE
-       bool "SiFive errata"
-       depends on !XIP_KERNEL
-       select RISCV_ALTERNATIVE
-       help
-         All SiFive errata Kconfig depend on this Kconfig. Disabling
-         this Kconfig will disable all SiFive errata. Please say "Y"
-         here if your platform uses SiFive CPU cores.
-
-         Otherwise, please say "N" here to avoid unnecessary overhead.
-
-config ERRATA_SIFIVE_CIP_453
-       bool "Apply SiFive errata CIP-453"
-       depends on ERRATA_SIFIVE && 64BIT
-       default y
-       help
-         This will apply the SiFive CIP-453 errata to add sign extension
-         to the $badaddr when exception type is instruction page fault
-         and instruction access fault.
-
-         If you don't know what to do here, say "Y".
-
-config ERRATA_SIFIVE_CIP_1200
-       bool "Apply SiFive errata CIP-1200"
-       depends on ERRATA_SIFIVE && 64BIT
-       default y
-       help
-         This will apply the SiFive CIP-1200 errata to repalce all
-         "sfence.vma addr" with "sfence.vma" to ensure that the addr
-         has been flushed from TLB.
-
-         If you don't know what to do here, say "Y".
-
-config ERRATA_THEAD
-       bool "T-HEAD errata"
-       depends on !XIP_KERNEL
-       select RISCV_ALTERNATIVE
-       help
-         All T-HEAD errata Kconfig depend on this Kconfig. Disabling
-         this Kconfig will disable all T-HEAD errata. Please say "Y"
-         here if your platform uses T-HEAD CPU cores.
-
-         Otherwise, please say "N" here to avoid unnecessary overhead.
-
-config ERRATA_THEAD_PBMT
-       bool "Apply T-Head memory type errata"
-       depends on ERRATA_THEAD && 64BIT && MMU
-       select RISCV_ALTERNATIVE_EARLY
-       default y
-       help
-         This will apply the memory type errata to handle the non-standard
-         memory type bits in page-table-entries on T-Head SoCs.
-
-         If you don't know what to do here, say "Y".
-
-config ERRATA_THEAD_CMO
-       bool "Apply T-Head cache management errata"
-       depends on ERRATA_THEAD && MMU
-       select RISCV_DMA_NONCOHERENT
-       default y
-       help
-         This will apply the cache management errata to handle the
-         non-standard handling on non-coherent operations on T-Head SoCs.
-
-         If you don't know what to do here, say "Y".
-
-config ERRATA_THEAD_PMU
-       bool "Apply T-Head PMU errata"
-       depends on ERRATA_THEAD && RISCV_PMU_SBI
-       default y
-       help
-         The T-Head C9xx cores implement a PMU overflow extension very
-         similar to the core SSCOFPMF extension.
-
-         This will apply the overflow errata to handle the non-standard
-         behaviour via the regular SBI PMU driver and interface.
-
-         If you don't know what to do here, say "Y".
-
-endmenu # "CPU errata selection"