drm/i915: move pch_ssc_use to display sub-struct under dpll

Move the display related member to the struct drm_i915_private display
sub-struct.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230117143946.2426043-2-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 2e85dd0ef4b536aa39f9d66a4bd2dfdf320ddf41..c0eb753112d5aaf3eecd295a5d5a366217a7ddbd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -122,6 +122,11 @@ struct intel_dpll {
                int nssc;
                int ssc;
        } ref_clks;
+
+       /*
+        * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
+        */
+       u8 pch_ssc_use;
 };
 
 struct intel_frontbuffer_tracking {

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1974eb580ed19812b1fafadb1f5597202e5bf67b..380368eff31a20f6d0a364098c0dc681900205bc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -618,7 +618,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
         * Try to set up the PCH reference clock once all DPLLs
         * that depend on it have been shut down.
         */
-       if (dev_priv->pch_ssc_use & BIT(id))
+       if (dev_priv->display.dpll.pch_ssc_use & BIT(id))
                intel_init_pch_refclk(dev_priv);
 }
 
@@ -636,7 +636,7 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
         * Try to set up the PCH reference clock once all DPLLs
         * that depend on it have been shut down.
         */
-       if (dev_priv->pch_ssc_use & BIT(id))
+       if (dev_priv->display.dpll.pch_ssc_use & BIT(id))
                intel_init_pch_refclk(dev_priv);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 08a94365b7d13b6a2be7e49588c76ffcb786c342..3657b2940702976088808ba8cfbab6df715f74fd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -467,24 +467,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
         * clock hierarchy. That would also allow us to do
         * clock bending finally.
         */
-       dev_priv->pch_ssc_use = 0;
+       dev_priv->display.dpll.pch_ssc_use = 0;
 
        if (spll_uses_pch_ssc(dev_priv)) {
                drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
-               dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
+               dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
        }
 
        if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
                drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
-               dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
+               dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
        }
 
        if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
                drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
-               dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
+               dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
        }
 
-       if (dev_priv->pch_ssc_use)
+       if (dev_priv->display.dpll.pch_ssc_use)
                return;
 
        if (has_fdi) {

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bedcd0891c48c8853248eed519e7a148981986b5..4e24d6f597d51c94c93f94a14ac5cb9b08c2c18b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -374,8 +374,6 @@ struct drm_i915_private {
                struct file *mmap_singleton;
        } gem;
 
-       u8 pch_ssc_use;
-
        /* For i915gm/i945gm vblank irq workaround */
        u8 vblank_enabled;