bnxt_en: Define basic P7 macros
authorMichael Chan <michael.chan@broadcom.com>
Fri, 1 Dec 2023 22:39:12 +0000 (14:39 -0800)
committerJakub Kicinski <kuba@kernel.org>
Mon, 4 Dec 2023 23:12:47 +0000 (15:12 -0800)
Repurpose the BNXT_FLAG_CHIP_SR2 flag by renaming it to
BNXT_FLAG_CHIP_P7 since the SR2 chip never went to production.  The SR2
statictics structure is also renamed for the P7 chip.  Define the basic
P7 doorbell bits (Epoch. Toggle, etc) and implement the Epoch bit
logic.  The next higher bit beyond the legal doorbell mask is the
Epoch bit used for doorbells on P7 chips.  This bit is used by the
chip to detect dropped doorbells.

The 57608 chip ID belonging to the P7 family is also defined.  Note
that the PCI ID is not added until the last patch in the series.

Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Link: https://lore.kernel.org/r/20231201223924.26955-4-michael.chan@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/broadcom/bnxt/bnxt.c
drivers/net/ethernet/broadcom/bnxt/bnxt.h
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

index 6f37b6ac89963e1165c856354d21c55eb6cbf149..829b2a6a05a092222677f7fbf02e3075d676cc89 100644 (file)
@@ -260,6 +260,10 @@ static bool bnxt_vf_pciid(enum board_idx idx)
        bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | DB_RING_IDX(db, idx),\
                    (db)->doorbell)
 
+#define BNXT_DB_NQ_P7(db, idx)                                         \
+       bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_MASK |             \
+                   DB_RING_IDX(db, idx), (db)->doorbell)
+
 #define BNXT_DB_CQ_ARM(db, idx)                                                \
        writel(DB_CP_REARM_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
 
@@ -269,7 +273,9 @@ static bool bnxt_vf_pciid(enum board_idx idx)
 
 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 {
-       if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
+       if (bp->flags & BNXT_FLAG_CHIP_P7)
+               BNXT_DB_NQ_P7(db, idx);
+       else if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
                BNXT_DB_NQ_P5(db, idx);
        else
                BNXT_DB_CQ(db, idx);
@@ -5784,7 +5790,7 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
                        if (BNXT_CHIP_P5(bp))
                                bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
                        else
-                               bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
+                               bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P7;
                }
        }
        hwrm_req_drop(bp, req);
@@ -6015,6 +6021,10 @@ static void bnxt_set_db_mask(struct bnxt *bp, struct bnxt_db_info *db,
                db->db_ring_mask = bp->cp_ring_mask;
                break;
        }
+       if (bp->flags & BNXT_FLAG_CHIP_P7) {
+               db->db_epoch_mask = db->db_ring_mask + 1;
+               db->db_epoch_shift = DBR_EPOCH_SFT - ilog2(db->db_epoch_mask);
+       }
 }
 
 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
@@ -6041,6 +6051,9 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
                        break;
                }
                db->db_key64 |= (u64)xid << DBR_XID_SFT;
+
+               if (bp->flags & BNXT_FLAG_CHIP_P7)
+                       db->db_key64 |= DBR_VALID;
        } else {
                db->doorbell = bp->bar1 + map_idx * 0x80;
                switch (ring_type) {
@@ -14014,8 +14027,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
        if (BNXT_CHIP_P5_PLUS(bp)) {
                bp->flags |= BNXT_FLAG_CHIP_P5_PLUS;
-               if (BNXT_CHIP_SR2(bp))
-                       bp->flags |= BNXT_FLAG_CHIP_SR2;
+               if (BNXT_CHIP_P7(bp))
+                       bp->flags |= BNXT_FLAG_CHIP_P7;
        }
 
        rc = bnxt_alloc_rss_indir_tbl(bp);
index 8a22b2d7ea94209c89d4fa776b8c6c3bc2d98133..40b26f7a0f5ea445c2201f608b5a3b8fc0086c85 100644 (file)
@@ -541,6 +541,8 @@ struct nqe_cn {
        #define NQ_CN_TYPE_SFT            0
        #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
        #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
+       #define NQ_CN_TOGGLE_MASK         0xc0UL
+       #define NQ_CN_TOGGLE_SFT          6
        __le16  reserved16;
        __le32  cq_handle_low;
        __le32  v;
@@ -561,6 +563,10 @@ struct nqe_cn {
 #define BNXT_SET_NQ_HDL(cpr)                                           \
        (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
 
+#define NQE_CN_TYPE(type)      ((type) & NQ_CN_TYPE_MASK)
+#define NQE_CN_TOGGLE(type)    (((type) & NQ_CN_TOGGLE_MASK) >>        \
+                                NQ_CN_TOGGLE_SFT)
+
 #define DB_IDX_MASK                                            0xffffff
 #define DB_IDX_VALID                                           (0x1 << 26)
 #define DB_IRQ_DIS                                             (0x1 << 27)
@@ -576,9 +582,14 @@ struct nqe_cn {
 
 /* 64-bit doorbell */
 #define DBR_INDEX_MASK                                 0x0000000000ffffffULL
+#define DBR_EPOCH_MASK                                 0x01000000UL
+#define DBR_EPOCH_SFT                                  24
+#define DBR_TOGGLE_MASK                                        0x06000000UL
+#define DBR_TOGGLE_SFT                                 25
 #define DBR_XID_MASK                                   0x000fffff00000000ULL
 #define DBR_XID_SFT                                    32
 #define DBR_PATH_L2                                    (0x1ULL << 56)
+#define DBR_VALID                                      (0x1ULL << 58)
 #define DBR_TYPE_SQ                                    (0x0ULL << 60)
 #define DBR_TYPE_RQ                                    (0x1ULL << 60)
 #define DBR_TYPE_SRQ                                   (0x2ULL << 60)
@@ -591,6 +602,7 @@ struct nqe_cn {
 #define DBR_TYPE_CQ_CUTOFF_ACK                         (0x9ULL << 60)
 #define DBR_TYPE_NQ                                    (0xaULL << 60)
 #define DBR_TYPE_NQ_ARM                                        (0xbULL << 60)
+#define DBR_TYPE_NQ_MASK                               (0xeULL << 60)
 #define DBR_TYPE_NULL                                  (0xfULL << 60)
 
 #define DB_PF_OFFSET_P5                                        0x10000
@@ -819,9 +831,17 @@ struct bnxt_db_info {
                u32             db_key32;
        };
        u32                     db_ring_mask;
+       u32                     db_epoch_mask;
+       u8                      db_epoch_shift;
 };
 
-#define DB_RING_IDX(db, idx)   ((idx) & (db)->db_ring_mask)
+#define DB_EPOCH(db, idx)      (((idx) & (db)->db_epoch_mask) <<       \
+                                ((db)->db_epoch_shift))
+
+#define DB_TOGGLE(tgl)         ((tgl) << DBR_TOGGLE_SFT)
+
+#define DB_RING_IDX(db, idx)   (((idx) & (db)->db_ring_mask) |         \
+                                DB_EPOCH(db, idx))
 
 struct bnxt_tx_ring_info {
        struct bnxt_napi        *bnapi;
@@ -1803,14 +1823,14 @@ struct bnxt {
 #define CHIP_NUM_57504         0x1751
 #define CHIP_NUM_57502         0x1752
 
+#define CHIP_NUM_57608         0x1760
+
 #define CHIP_NUM_58802         0xd802
 #define CHIP_NUM_58804         0xd804
 #define CHIP_NUM_58808         0xd808
 
        u8                      chip_rev;
 
-#define CHIP_NUM_58818         0xd818
-
 #define BNXT_CHIP_NUM_5730X(chip_num)          \
        ((chip_num) >= CHIP_NUM_57301 &&        \
         (chip_num) <= CHIP_NUM_57304)
@@ -1888,7 +1908,7 @@ struct bnxt {
                                         BNXT_FLAG_ROCEV2_CAP)
        #define BNXT_FLAG_NO_AGG_RINGS  0x20000
        #define BNXT_FLAG_RX_PAGE_MODE  0x40000
-       #define BNXT_FLAG_CHIP_SR2      0x80000
+       #define BNXT_FLAG_CHIP_P7       0x80000
        #define BNXT_FLAG_MULTI_HOST    0x100000
        #define BNXT_FLAG_DSN_VALID     0x200000
        #define BNXT_FLAG_DOUBLE_DB     0x400000
@@ -1918,8 +1938,8 @@ struct bnxt {
                                  (bp)->max_tpa_v2) && !is_kdump_kernel())
 #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
 
-#define BNXT_CHIP_SR2(bp)                      \
-       ((bp)->chip_num == CHIP_NUM_58818)
+#define BNXT_CHIP_P7(bp)                       \
+       ((bp)->chip_num == CHIP_NUM_57608)
 
 #define BNXT_CHIP_P5(bp)                       \
        ((bp)->chip_num == CHIP_NUM_57508 ||    \
@@ -1928,7 +1948,7 @@ struct bnxt {
 
 /* Chip class phase 5 */
 #define BNXT_CHIP_P5_PLUS(bp)                  \
-       (BNXT_CHIP_P5(bp) || BNXT_CHIP_SR2(bp))
+       (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
 
 /* Chip class phase 4.x */
 #define BNXT_CHIP_P4(bp)                       \
@@ -2272,15 +2292,15 @@ struct bnxt {
 #define BNXT_NUM_TX_RING_STATS                 8
 #define BNXT_NUM_TPA_RING_STATS                        4
 #define BNXT_NUM_TPA_RING_STATS_P5             5
-#define BNXT_NUM_TPA_RING_STATS_P5_SR2         6
+#define BNXT_NUM_TPA_RING_STATS_P7             6
 
 #define BNXT_RING_STATS_SIZE_P5                                        \
        ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
          BNXT_NUM_TPA_RING_STATS_P5) * 8)
 
-#define BNXT_RING_STATS_SIZE_P5_SR2                            \
+#define BNXT_RING_STATS_SIZE_P7                                        \
        ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
-         BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
+         BNXT_NUM_TPA_RING_STATS_P7) * 8)
 
 #define BNXT_GET_RING_STATS64(sw, counter)             \
        (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
index b0cea5b600cc9d44bff8062fc7c93c520f21f3bb..99c8b15bdfbe8bb72dd4d0f7d325c3138752fc88 100644 (file)
@@ -513,7 +513,7 @@ static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
                if (bp->max_tpa_v2) {
                        if (BNXT_CHIP_P5(bp))
                                return BNXT_NUM_TPA_RING_STATS_P5;
-                       return BNXT_NUM_TPA_RING_STATS_P5_SR2;
+                       return BNXT_NUM_TPA_RING_STATS_P7;
                }
                return BNXT_NUM_TPA_RING_STATS;
        }