ASoC: tegra20: ac97: Add reset control
authorDmitry Osipenko <digetx@gmail.com>
Sun, 14 Mar 2021 15:44:43 +0000 (18:44 +0300)
committerMark Brown <broonie@kernel.org>
Thu, 18 Mar 2021 13:49:30 +0000 (13:49 +0000)
Tegra20 AC97 driver doesn't manage the AC97 controller reset, relying on
implicit deassertion of the reset by tegra-clk driver, which needs to be
fixed since this behaviour is unacceptable by other Tegra drivers. Add
explicit reset control to the Tegra20 AC97 driver.

Note that AC97 reset was always specified in Tegra20 device-tree, hence
DTB ABI changes aren't required.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210314154459.15375-2-digetx@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/tegra/tegra20_ac97.c
sound/soc/tegra/tegra20_ac97.h

index 06c728ae17edc91946eb62bb8ec3d4f4a0839f5b..c454a34c15c4c46f3808f423abedf5f9057d655f 100644 (file)
@@ -21,6 +21,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -313,6 +314,12 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
        }
        dev_set_drvdata(&pdev->dev, ac97);
 
+       ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
+       if (IS_ERR(ac97->reset)) {
+               dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
+               return PTR_ERR(ac97->reset);
+       }
+
        ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
        if (IS_ERR(ac97->clk_ac97)) {
                dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
@@ -364,12 +371,26 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
        ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
        ac97->playback_dma_data.maxburst = 4;
 
+       ret = reset_control_assert(ac97->reset);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret);
+               goto err_clk_put;
+       }
+
        ret = clk_prepare_enable(ac97->clk_ac97);
        if (ret) {
                dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
                goto err_clk_put;
        }
 
+       usleep_range(10, 100);
+
+       ret = reset_control_deassert(ac97->reset);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret);
+               goto err_clk_disable_unprepare;
+       }
+
        ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
        if (ret) {
                dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
index e467cd1ff2ca4cb30c61d82e7c06a56513db3fe4..870ea09ff3010d6a9088fe5fcf8b19b588a24e24 100644 (file)
@@ -78,6 +78,7 @@ struct tegra20_ac97 {
        struct clk *clk_ac97;
        struct snd_dmaengine_dai_dma_data capture_dma_data;
        struct snd_dmaengine_dai_dma_data playback_dma_data;
+       struct reset_control *reset;
        struct regmap *regmap;
        int reset_gpio;
        int sync_gpio;