arm64: tegra: Add node for CBB 1.0 on Tegra194

Add device tree nodes to enable error handling on the Control Backbone
(CBB). Tegra194 uses CBB version 1.0.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9566c6388ed9fca087432e1cf3abc7c0f3b35a26..5321e3e60b24d54752b1d1ecb1f4c7fe557a4a66 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -23,7 +23,7 @@
                #size-cells = <1>;
                ranges = <0x0 0x0 0x0 0x40000000>;
 
-               misc@100000 {
+               apbmisc: misc@100000 {
                        compatible = "nvidia,tegra194-misc";
                        reg = <0x00100000 0xf000>,
                              <0x0010f000 0x1000>;
@@ -88,6 +88,27 @@
                        gpio-controller;
                };
 
+               cbb-noc@2300000 {
+                       compatible = "nvidia,tegra194-cbb-noc";
+                       reg = <0x02300000 0x1000>;
+                       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+                       nvidia,axi2apb = <&axi2apb>;
+                       nvidia,apbmisc = <&apbmisc>;
+                       status = "okay";
+               };
+
+               axi2apb: axi2apb@2390000 {
+                       compatible = "nvidia,tegra194-axi2apb";
+                       reg = <0x2390000 0x1000>,
+                             <0x23a0000 0x1000>,
+                             <0x23b0000 0x1000>,
+                             <0x23c0000 0x1000>,
+                             <0x23d0000 0x1000>,
+                             <0x23e0000 0x1000>;
+                       status = "okay";
+               };
+
                ethernet@2490000 {
                        compatible = "nvidia,tegra194-eqos",
                                     "nvidia,tegra186-eqos",
@@ -1483,6 +1504,26 @@
                        #phy-cells = <0>;
                };
 
+               sce-noc@b600000 {
+                       compatible = "nvidia,tegra194-sce-noc";
+                       reg = <0xb600000 0x1000>;
+                       interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                       nvidia,axi2apb = <&axi2apb>;
+                       nvidia,apbmisc = <&apbmisc>;
+                       status = "okay";
+               };
+
+               rce-noc@be00000 {
+                       compatible = "nvidia,tegra194-rce-noc";
+                       reg = <0xbe00000 0x1000>;
+                       interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                       nvidia,axi2apb = <&axi2apb>;
+                       nvidia,apbmisc = <&apbmisc>;
+                       status = "okay";
+               };
+
                hsp_aon: hsp@c150000 {
                        compatible = "nvidia,tegra194-hsp";
                        reg = <0x0c150000 0x90000>;
@@ -1617,6 +1658,25 @@
 
                };
 
+               aon-noc@c600000 {
+                       compatible = "nvidia,tegra194-aon-noc";
+                       reg = <0xc600000 0x1000>;
+                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                       nvidia,apbmisc = <&apbmisc>;
+                       status = "okay";
+               };
+
+               bpmp-noc@d600000 {
+                       compatible = "nvidia,tegra194-bpmp-noc";
+                       reg = <0xd600000 0x1000>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                       nvidia,axi2apb = <&axi2apb>;
+                       nvidia,apbmisc = <&apbmisc>;
+                       status = "okay";
+               };
+
                iommu@10000000 {
                        compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
                        reg = <0x10000000 0x800000>;