hw/riscv: Move sifive_test model to hw/misc

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index fa3d0f4723070fe7b2a1c3e468f961a6529c4ac2..31854561105707c6dba6df53d4cc6ab26584a62c 100644 (file)
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,6 +134,9 @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_TEST
+    bool
+
 config SIFIVE_E_PRCI
     bool
 

diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 018a88c670dfc0b0202bbdf560c4684c5a8ff2e6..bd24132757aef172f4d8efc8c04873bb69d6da35 100644 (file)
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))

diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c
new file mode 100644 (file)
index 0000000..2deb207
--- /dev/null
+++ b/hw/misc/sifive_test.c
@@ -0,0 +1,100 @@
+/*
+ * QEMU SiFive Test Finisher
+ *
+ * Copyright (c) 2018 SiFive, Inc.
+ *
+ * Test finisher memory mapped device used to exit simulation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "sysemu/runstate.h"
+#include "hw/hw.h"
+#include "hw/misc/sifive_test.h"
+
+static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    return 0;
+}
+
+static void sifive_test_write(void *opaque, hwaddr addr,
+           uint64_t val64, unsigned int size)
+{
+    if (addr == 0) {
+        int status = val64 & 0xffff;
+        int code = (val64 >> 16) & 0xffff;
+        switch (status) {
+        case FINISHER_FAIL:
+            exit(code);
+        case FINISHER_PASS:
+            exit(0);
+        case FINISHER_RESET:
+            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            return;
+        default:
+            break;
+        }
+    }
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
+                  __func__, (int)addr, val64);
+}
+
+static const MemoryRegionOps sifive_test_ops = {
+    .read = sifive_test_read,
+    .write = sifive_test_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 2,
+        .max_access_size = 4
+    }
+};
+
+static void sifive_test_init(Object *obj)
+{
+    SiFiveTestState *s = SIFIVE_TEST(obj);
+
+    memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
+                          TYPE_SIFIVE_TEST, 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static const TypeInfo sifive_test_info = {
+    .name          = TYPE_SIFIVE_TEST,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFiveTestState),
+    .instance_init = sifive_test_init,
+};
+
+static void sifive_test_register_types(void)
+{
+    type_register_static(&sifive_test_info);
+}
+
+type_init(sifive_test_register_types)
+
+
+/*
+ * Create Test device.
+ */
+DeviceState *sifive_test_create(hwaddr addr)
+{
+    DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+    return dev;
+}

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0461578a6b5583e2c61ee5224979d4652d76a0e..8e0710001bca672ba65f45a4c662ec7f25e0a82f 100644 (file)
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -61,6 +61,7 @@ config RISCV_VIRT
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_PLIC
+    select SIFIVE_TEST
 
 config MICROCHIP_PFSOC
     bool

diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 967572d4f6adcd2d58a937638aa91bc477a9ebd3..f762623288fcaeedf9b1652571e1e99f8cdcfeeb 100644 (file)
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))

diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
deleted file mode 100644 (file)
index 8c70dd6..0000000
--- a/hw/riscv/sifive_test.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * QEMU SiFive Test Finisher
- *
- * Copyright (c) 2018 SiFive, Inc.
- *
- * Test finisher memory mapped device used to exit simulation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "hw/sysbus.h"
-#include "qapi/error.h"
-#include "qemu/log.h"
-#include "qemu/module.h"
-#include "sysemu/runstate.h"
-#include "hw/hw.h"
-#include "hw/riscv/sifive_test.h"
-
-static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
-{
-    return 0;
-}
-
-static void sifive_test_write(void *opaque, hwaddr addr,
-           uint64_t val64, unsigned int size)
-{
-    if (addr == 0) {
-        int status = val64 & 0xffff;
-        int code = (val64 >> 16) & 0xffff;
-        switch (status) {
-        case FINISHER_FAIL:
-            exit(code);
-        case FINISHER_PASS:
-            exit(0);
-        case FINISHER_RESET:
-            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-            return;
-        default:
-            break;
-        }
-    }
-    qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
-                  __func__, (int)addr, val64);
-}
-
-static const MemoryRegionOps sifive_test_ops = {
-    .read = sifive_test_read,
-    .write = sifive_test_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid = {
-        .min_access_size = 2,
-        .max_access_size = 4
-    }
-};
-
-static void sifive_test_init(Object *obj)
-{
-    SiFiveTestState *s = SIFIVE_TEST(obj);
-
-    memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
-                          TYPE_SIFIVE_TEST, 0x1000);
-    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-}
-
-static const TypeInfo sifive_test_info = {
-    .name          = TYPE_SIFIVE_TEST,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(SiFiveTestState),
-    .instance_init = sifive_test_init,
-};
-
-static void sifive_test_register_types(void)
-{
-    type_register_static(&sifive_test_info);
-}
-
-type_init(sifive_test_register_types)
-
-
-/*
- * Create Test device.
- */
-DeviceState *sifive_test_create(hwaddr addr)
-{
-    DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-    return dev;
-}

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0caab8e050d4df5c2c6ebf1e45d7cef64268aeab..41bd2f38ba181a6178485efe8493c3ff9b884f98 100644 (file)
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"

diff --git a/include/hw/misc/sifive_test.h b/include/hw/misc/sifive_test.h
new file mode 100644 (file)
index 0000000..1ec416a
--- /dev/null
+++ b/include/hw/misc/sifive_test.h
@@ -0,0 +1,45 @@
+/*
+ * QEMU Test Finisher interface
+ *
+ * Copyright (c) 2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_TEST_H
+#define HW_SIFIVE_TEST_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_SIFIVE_TEST "riscv.sifive.test"
+
+#define SIFIVE_TEST(obj) \
+    OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
+
+typedef struct SiFiveTestState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion mmio;
+} SiFiveTestState;
+
+enum {
+    FINISHER_FAIL = 0x3333,
+    FINISHER_PASS = 0x5555,
+    FINISHER_RESET = 0x7777
+};
+
+DeviceState *sifive_test_create(hwaddr addr);
+
+#endif

diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
deleted file mode 100644 (file)
index 1ec416a..0000000
--- a/include/hw/riscv/sifive_test.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * QEMU Test Finisher interface
- *
- * Copyright (c) 2018 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_TEST_H
-#define HW_SIFIVE_TEST_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_TEST "riscv.sifive.test"
-
-#define SIFIVE_TEST(obj) \
-    OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
-
-typedef struct SiFiveTestState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-} SiFiveTestState;
-
-enum {
-    FINISHER_FAIL = 0x3333,
-    FINISHER_PASS = 0x5555,
-    FINISHER_RESET = 0x7777
-};
-
-DeviceState *sifive_test_create(hwaddr addr);
-
-#endif