ARM: dts: am33xx-clocks: add spread spectrum support

Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index dced92a8970e65e7786dc335f17e8cc0808dabc9..b7b7106f2deedc97eecb35f2b9b7c43b60f3a67a 100644 (file)
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -164,7 +164,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0490>, <0x045c>, <0x0468>;
+               reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
        };
 
        dpll_core_x2_ck: dpll_core_x2_ck {
@@ -204,7 +204,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0488>, <0x0420>, <0x042c>;
+               reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
        };
 
        dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -220,7 +220,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0494>, <0x0434>, <0x0440>;
+               reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
        };
 
        dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@@ -244,7 +244,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x0498>, <0x0448>, <0x0454>;
+               reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
        };
 
        dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@@ -261,7 +261,7 @@
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x048c>, <0x0470>, <0x049c>;
+               reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
        };
 
        dpll_per_m2_ck: dpll_per_m2_ck@4ac {