riscv: dts: sifive: convert isa detection to new properties

Convert the fu540 and fu740 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 24bba83bec77712f128202e97a2cd483cfabcf1a..156330a9bbf3860c149ec0ccea1c97fb084cecf0 100644 (file)
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,9 @@
                        i-cache-size = <16384>;
                        reg = <0>;
                        riscv,isa = "rv64imac";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
                        status = "disabled";
                        cpu0_intc: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -53,6 +56,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <1>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu1_intc: interrupt-controller {
@@ -77,6 +83,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <2>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu2_intc: interrupt-controller {
@@ -101,6 +110,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <3>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu3_intc: interrupt-controller {
@@ -125,6 +137,9 @@
                        mmu-type = "riscv,sv39";
                        reg = <4>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        next-level-cache = <&l2cache>;
                        cpu4_intc: interrupt-controller {

diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index 5235fd1c9cb6773d2f23562fe999ffa0ca21dc6b..6150f3397bff9269767b190d961024a98b367ddc 100644 (file)
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -31,6 +31,9 @@
                        next-level-cache = <&ccache>;
                        reg = <0x0>;
                        riscv,isa = "rv64imac";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
                        status = "disabled";
                        cpu0_intc: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -55,6 +58,9 @@
                        next-level-cache = <&ccache>;
                        reg = <0x1>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        cpu1_intc: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -79,6 +85,9 @@
                        next-level-cache = <&ccache>;
                        reg = <0x2>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        cpu2_intc: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -103,6 +112,9 @@
                        next-level-cache = <&ccache>;
                        reg = <0x3>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        cpu3_intc: interrupt-controller {
                                #interrupt-cells = <1>;
@@ -127,6 +139,9 @@
                        next-level-cache = <&ccache>;
                        reg = <0x4>;
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
                        cpu4_intc: interrupt-controller {
                                #interrupt-cells = <1>;