return ret;
priv->clkin = devm_clk_get(&pdev->dev, "clkin");
- if (IS_ERR(priv->clkin)) {
- dev_err(&pdev->dev, "failed to get clkin\n");
- return PTR_ERR(priv->clkin);
- }
+ if (IS_ERR(priv->clkin))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkin),
+ "failed to get clkin\n");
priv->core_clk = devm_clk_get(&pdev->dev, "core");
- if (IS_ERR(priv->core_clk)) {
- dev_err(&pdev->dev, "failed to get core clk\n");
- return PTR_ERR(priv->core_clk);
- }
+ if (IS_ERR(priv->core_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk),
+ "failed to get core clk\n");
priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
if (IS_ERR(priv->adc_clk)) {
- if (PTR_ERR(priv->adc_clk) == -ENOENT) {
+ if (PTR_ERR(priv->adc_clk) == -ENOENT)
priv->adc_clk = NULL;
- } else {
- dev_err(&pdev->dev, "failed to get adc clk\n");
- return PTR_ERR(priv->adc_clk);
- }
+ else
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk),
+ "failed to get adc clk\n");
}
priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
if (IS_ERR(priv->adc_sel_clk)) {
- if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
+ if (PTR_ERR(priv->adc_sel_clk) == -ENOENT)
priv->adc_sel_clk = NULL;
- } else {
- dev_err(&pdev->dev, "failed to get adc_sel clk\n");
- return PTR_ERR(priv->adc_sel_clk);
- }
+ else
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk),
+ "failed to get adc_sel clk\n");
}
/* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
}
priv->vref = devm_regulator_get(&pdev->dev, "vref");
- if (IS_ERR(priv->vref)) {
- dev_err(&pdev->dev, "failed to get vref regulator\n");
- return PTR_ERR(priv->vref);
- }
+ if (IS_ERR(priv->vref))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
+ "failed to get vref regulator\n");
priv->calibscale = MILLION;