clk: imx: correct pfdv2 gate_bit/vld_bit operations

The operations of pfdv2 gate_bit/valid_bit are incorrect,
they are defined as u8 for bit offset, but gate_bit is
actually assigned as mask which could be 32 bit long and
it causes overflow, and vld_bit is assigned as bit offset
based on incorrect gate_bit value, it causes incorrect
pfd clock gate status in clock tree, this patch fixes the
issue by assigning them as correct bit offset.

Fixes: 9fcb6be3b6c9 ("clk: imx: add pfdv2 support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
index 7e9134b205abc41a1ef89d243502875ab56e5762..fb567dcc21185bb714982d5f3999d6d6065e944f 100644 (file)
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -43,7 +43,7 @@ static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
 {
        u32 val;
 
-       return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+       return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
                                  0, LOCK_TIMEOUT_US);
 }
 
@@ -55,7 +55,7 @@ static int clk_pfdv2_enable(struct clk_hw *hw)
 
        spin_lock_irqsave(&pfd_lock, flags);
        val = readl_relaxed(pfd->reg);
-       val &= ~pfd->gate_bit;
+       val &= ~(1 << pfd->gate_bit);
        writel_relaxed(val, pfd->reg);
        spin_unlock_irqrestore(&pfd_lock, flags);
 
@@ -70,7 +70,7 @@ static void clk_pfdv2_disable(struct clk_hw *hw)
 
        spin_lock_irqsave(&pfd_lock, flags);
        val = readl_relaxed(pfd->reg);
-       val |= pfd->gate_bit;
+       val |= (1 << pfd->gate_bit);
        writel_relaxed(val, pfd->reg);
        spin_unlock_irqrestore(&pfd_lock, flags);
 }
@@ -123,7 +123,7 @@ static int clk_pfdv2_is_enabled(struct clk_hw *hw)
 {
        struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
 
-       if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+       if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
                return 0;
 
        return 1;
@@ -180,7 +180,7 @@ struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
                return ERR_PTR(-ENOMEM);
 
        pfd->reg = reg;
-       pfd->gate_bit = 1 << ((idx + 1) * 8 - 1);
+       pfd->gate_bit = (idx + 1) * 8 - 1;
        pfd->vld_bit = pfd->gate_bit - 1;
        pfd->frac_off = idx * 8;