Revert "drm/amd/display: Enable CM low mem power optimization"

This reverts commit fcfc6ceec3ebb725a0d6381a1120e7cd546e1df4.

[why]
Flickering observed. Regression search pointed to this being
the offending commit.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 1a2adb3547182bdff5a55c2391d91f225673103e..994b21ed272f175318a0b3295ac1c1e052a6b95d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -71,24 +71,21 @@ void mpc32_power_on_blnd_lut(
 {
        struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 
-/*
        if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
                if (power_on) {
                        REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
                        REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
                } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
-                       //TODO: change to mpc
-                       dpp_base->ctx->dc->optimized_required = true;
-                       dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
+                       ASSERT(false);
+                       /* TODO: change to mpc
+                        *  dpp_base->ctx->dc->optimized_required = true;
+                        *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
+                        */
                }
        } else {
                REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
                                MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
        }
-*/
-
-       REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
-                       MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
 }
 
 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 0d5a03c6d812a586964910be486de8e9c379d6da..53eefba0b9dce1338ff8be40c7c0b47daf78ef4e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -736,7 +736,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .i2c = true,
                        .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
                        .dscl = true,
-                       .cm = true,
+                       .cm = false,
                        .mpc = true,
                        .optc = true,
                        .vpg = true,