wifi: iwlwifi: add support for SNPS DPHYIP region type
authorDaniel Gabay <daniel.gabay@intel.com>
Tue, 17 Oct 2023 09:16:42 +0000 (12:16 +0300)
committerJohannes Berg <johannes.berg@intel.com>
Mon, 23 Oct 2023 10:48:28 +0000 (12:48 +0200)
Add the required logic for parsing and dumping this new region.

Signed-off-by: Daniel Gabay <daniel.gabay@intel.com>
Signed-off-by: Gregory Greenman <gregory.greenman@intel.com>
Link: https://lore.kernel.org/r/20231017115047.c859539194e7.I965482de2871e28b09f4572f1aa87ae4e3b366be@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/intel/iwlwifi/fw/api/dbg-tlv.h
drivers/net/wireless/intel/iwlwifi/fw/dbg.c
drivers/net/wireless/intel/iwlwifi/iwl-prph.h

index fb421500f2610b213b806eba96e78a13fb69c41a..394747deb269805c94f60f7bddf3b5674df5ed14 100644 (file)
@@ -159,6 +159,7 @@ struct iwl_fw_ini_region_internal_buffer {
  *     &IWL_FW_INI_REGION_PAGING, &IWL_FW_INI_REGION_CSR,
  *     &IWL_FW_INI_REGION_DRAM_IMR and &IWL_FW_INI_REGION_PCI_IOSF_CONFIG
  *     &IWL_FW_INI_REGION_DBGI_SRAM, &FW_TLV_DEBUG_REGION_TYPE_DBGI_SRAM,
+ *     &IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP,
  * @dev_addr_range: device address range configuration. Used by
  *     &IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE and
  *     &IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE
@@ -392,6 +393,7 @@ enum iwl_fw_ini_buffer_location {
  * @IWL_FW_INI_REGION_DBGI_SRAM: periphery registers of DBGI SRAM
  * @IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE: a range of periphery registers of MAC
  * @IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE: a range of periphery registers of PHY
+ * @IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP: periphery registers of SNPS DPHYIP
  * @IWL_FW_INI_REGION_NUM: number of region types
  */
 enum iwl_fw_ini_region_type {
@@ -416,6 +418,7 @@ enum iwl_fw_ini_region_type {
        IWL_FW_INI_REGION_DBGI_SRAM,
        IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE,
        IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE,
+       IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP,
        IWL_FW_INI_REGION_NUM
 }; /* FW_TLV_DEBUG_REGION_TYPE_API_E */
 
index a20be36428485cb1cb60e65d2fe46ca24a951968..3975a53a9f2099a4aaf42e0488e605cf79df6b50 100644 (file)
@@ -1416,6 +1416,53 @@ out:
        return sizeof(*range) + le32_to_cpu(range->range_data_size);
 }
 
+static int
+iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
+                                  struct iwl_dump_ini_region_data *reg_data,
+                                  void *range_ptr, u32 range_len, int idx)
+{
+       struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
+       struct iwl_fw_ini_error_dump_range *range = range_ptr;
+       __le32 *val = range->data;
+       __le32 offset = reg->dev_addr.offset;
+       u32 indirect_rd_wr_addr = DPHYIP_INDIRECT;
+       u32 addr = le32_to_cpu(reg->addrs[idx]);
+       u32 dphy_state, dphy_addr, prph_val;
+       int i;
+
+       range->internal_base_addr = cpu_to_le32(addr);
+       range->range_data_size = reg->dev_addr.size;
+
+       if (!iwl_trans_grab_nic_access(fwrt->trans))
+               return -EBUSY;
+
+       indirect_rd_wr_addr += le32_to_cpu(offset);
+
+       dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
+       dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
+
+       for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
+               if (dphy_state == HBUS_TIMEOUT ||
+                   (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
+                   WFPM_PHYRF_STATE_ON) {
+                       *val++ = cpu_to_le32(WFPM_DPHY_OFF);
+                       continue;
+               }
+
+               iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr,
+                                      addr + i);
+               /* wait a bit for value to be ready in register */
+               udelay(1);
+               prph_val = iwl_read_prph_no_grab(fwrt->trans,
+                                                indirect_rd_wr_addr);
+               *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >>
+                                    DPHYIP_INDIRECT_RD_SHIFT);
+       }
+
+       iwl_trans_release_nic_access(fwrt->trans);
+       return sizeof(*range) + le32_to_cpu(range->range_data_size);
+}
+
 struct iwl_ini_rxf_data {
        u32 fifo_num;
        u32 size;
@@ -2537,6 +2584,12 @@ static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
                .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header,
                .fill_range = iwl_dump_ini_dbgi_sram_iter,
        },
+       [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = {
+               .get_num_of_ranges = iwl_dump_ini_mem_ranges,
+               .get_size = iwl_dump_ini_mem_get_size,
+               .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
+               .fill_range = iwl_dump_ini_prph_snps_dphyip_iter,
+       },
 };
 
 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
@@ -2580,7 +2633,8 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
                        continue;
 
                if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY ||
-                    reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE) &&
+                    reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE ||
+                    reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) &&
                    tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
                        IWL_WARN(fwrt,
                                 "WRT: trying to collect phy prph at time point: %d, skipping\n",
index da035dbfbdb089923b735723619e129b1db43127..dd32c287b98361d108a771bde82889a4e7d10cb9 100644 (file)
@@ -516,4 +516,8 @@ enum {
 #define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC
 #define WFPM_LMAC2_PD_RE_READ BIT(31)
 
+#define DPHYIP_INDIRECT                        0xA2D800
+#define DPHYIP_INDIRECT_RD_MSK         0xFF000000
+#define DPHYIP_INDIRECT_RD_SHIFT       24
+
 #endif                         /* __iwl_prph_h__ */