ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE

With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.

Let's also add a comment for the clocksel clock that matches the
documentation.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
index e021632a18efa82cd1e5b8bbd40b48e7b7c6c296..2c037a8ce94eb2266a3070863c20e0649c547bb0 100644 (file)
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -894,15 +894,23 @@
                clock-div = <1>;
        };
 
-       l3_iclk_div: clock-l3-iclk-div-4@100 {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clock-output-names = "l3_iclk_div";
-               ti,max-div = <2>;
-               ti,bit-shift = <4>;
-               reg = <0x0100>;
-               clocks = <&dpll_core_h12x2_ck>;
-               ti,index-power-of-two;
+       /* CM_CLKSEL_CORE */
+       clock@100 {
+               compatible = "ti,clksel";
+               reg = <0x100>;
+               #clock-cells = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               l3_iclk_div: clock@4 {
+                       reg = <4>;
+                       compatible = "ti,divider-clock";
+                       clock-output-names = "l3_iclk_div";
+                       ti,max-div = <2>;
+                       clocks = <&dpll_core_h12x2_ck>;
+                       ti,index-power-of-two;
+                       #clock-cells = <0>;
+               };
        };
 
        l4_root_clk_div: clock-l4-root-clk-div {