arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider

Add Operation State Manager (OSM) L3 interconnect provider node on
SM8150 SoCs.

Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200801123049.32398-7-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8f26df1651cd576d19e4fbf51f4b0f2e9f7433dc..f0a872e02686d7dcb331d6c4eda43b1d25490d50 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -1183,6 +1184,16 @@
                        };
                };
 
+               osm_l3: interconnect@18321000 {
+                       compatible = "qcom,sm8150-osm-l3";
+                       reg = <0 0x18321000 0 0x1400>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #interconnect-cells = <1>;
+               };
+
                cpufreq_hw: cpufreq@18323000 {
                        compatible = "qcom,cpufreq-hw";
                        reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,