drm/i915/xelpmp: Add multicast steering for media GT

MTL's media IP (Xe_LPM+) only has a single type of steering ("OAADDRM")
which selects between media slice 0 and media slice 1.  We'll always
steer to media slice 0 unless it is fused off (which is the case when
VD0, VE0, and SFC0 are all reported as unavailable).

Bspec: 67789
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-15-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 23a1ef9659bfee312803de8eb43374293411d2f9..0d2811724b00feab18d1ead9a999d688b4314bd8 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -42,6 +42,7 @@ static const char * const intel_steering_types[] = {
        "LNCF",
        "GAM",
        "DSS",
+       "OADDRM",
        "INSTANCE 0",
 };
 
@@ -129,6 +130,11 @@ static const struct intel_mmio_range xelpg_dss_steering_table[] = {
        { 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
 };
 
+static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
+       { 0x393200, 0x39323F },
+       { 0x393400, 0x3934FF },
+};
+
 void intel_gt_mcr_init(struct intel_gt *gt)
 {
        struct drm_i915_private *i915 = gt->i915;
@@ -151,8 +157,9 @@ void intel_gt_mcr_init(struct intel_gt *gt)
                        drm_warn(&i915->drm, "mslice mask all zero!\n");
        }
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
-           gt->type == GT_PRIMARY) {
+       if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
+               gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
+       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
                fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
                                     intel_uncore_read(gt->uncore, XEHP_FUSE4));
 
@@ -514,6 +521,13 @@ static void get_nonterminated_steering(struct intel_gt *gt,
                *group = 0;
                *instance = 0;
                break;
+       case OADDRM:
+               if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0))
+                       *group = 0;
+               else
+                       *group = 1;
+               *instance = 0;
+               break;
        default:
                MISSING_CASE(type);
                *group = 0;

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0bb73d110a842d8c1e1bcfea26f65af3ed51dbc4..64aa2ba624fc097d362b616a96bb5766083fdb08 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -61,6 +61,7 @@ enum intel_steering_type {
        LNCF,
        GAM,
        DSS,
+       OADDRM,
 
        /*
         * On some platforms there are multiple types of MCR registers that

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 711a319358578f98d2ccde24df8fc72cf5a1ef8c..bae960486872f874a9e909fd7b9d803840e96bc4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1598,14 +1598,27 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
        debug_dump_steering(gt);
 }
 
+static void
+xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+       /* FIXME: Actual workarounds will be added in future patch(es) */
+
+       debug_dump_steering(gt);
+}
+
 static void
 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = gt->i915;
 
-       /* FIXME: Media GT handling will be added in an upcoming patch */
-       if (gt->type == GT_MEDIA)
+       if (gt->type == GT_MEDIA) {
+               if (MEDIA_VER(i915) >= 13)
+                       xelpmp_gt_workarounds_init(gt, wal);
+               else
+                       MISSING_CASE(MEDIA_VER(i915));
+
                return;
+       }
 
        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
                xelpg_gt_workarounds_init(gt, wal);