arm64: dts: add pcie nodes for MT2712

This patch add device node for mt2712 pcie.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e8afb5431fcbb7886c4760c97c0fdb46d34f82e4..976d92a9473889f4d3dfa4b4d0bd1473205b1c36 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -791,6 +791,69 @@
                };
        };
 
+       pcie: pcie@11700000 {
+               compatible = "mediatek,mt2712-pcie";
+               device_type = "pci";
+               reg = <0 0x11700000 0 0x1000>,
+                     <0 0x112ff000 0 0x1000>;
+               reg-names = "port0", "port1";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+                        <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+                        <&pericfg CLK_PERI_PCIE0>,
+                        <&pericfg CLK_PERI_PCIE1>;
+               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+               phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1";
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+
+               pcie0: pcie@0,0 {
+                       device_type = "pci";
+                       status = "disabled";
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                       <0 0 0 2 &pcie_intc0 1>,
+                                       <0 0 0 3 &pcie_intc0 2>,
+                                       <0 0 0 4 &pcie_intc0 3>;
+                       pcie_intc0: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               pcie1: pcie@1,0 {
+                       device_type = "pci";
+                       status = "disabled";
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                       <0 0 0 2 &pcie_intc1 1>,
+                                       <0 0 0 3 &pcie_intc1 2>,
+                                       <0 0 0 4 &pcie_intc1 3>;
+                       pcie_intc1: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
+
        mfgcfg: syscon@13000000 {
                compatible = "mediatek,mt2712-mfgcfg", "syscon";
                reg = <0 0x13000000 0 0x1000>;