arm64: dts: renesas: r9a07g044: Add SDHI nodes

Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007155451.10654-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 1f01737d2def9c1ed21a1670d8321f98207de319..0b0372a025158faa9b223bfe46e28a64c8932333 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -456,6 +456,38 @@
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };
 
+               sdhi0: mmc@11c00000  {
+                       compatible = "renesas,sdhi-r9a07g044",
+                                    "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x11c00000 0 0x10000>;
+                       interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
+                                <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
+                                <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
+                       clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+                       resets = <&cpg R9A07G044_SDHI0_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               sdhi1: mmc@11c10000 {
+                       compatible = "renesas,sdhi-r9a07g044",
+                                    "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x11c10000 0 0x10000>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
+                                <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
+                                <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
+                       clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+                       resets = <&cpg R9A07G044_SDHI1_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                phyrst: usbphy-ctrl@11c40000 {
                        compatible = "renesas,r9a07g044-usbphy-ctrl",
                                     "renesas,rzg2l-usbphy-ctrl";