drm/amd/display: PME sw wa to support waking AZ D3
authorCharlene Liu <charlene.liu@amd.com>
Wed, 13 Dec 2017 18:41:42 +0000 (13:41 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 19 Feb 2018 19:17:17 +0000 (14:17 -0500)
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

index a3742827157361ac0c3c57733eb845cd34ea4720..2b791b25b3a6e1d4fc1783f0d2be960561520209 100644 (file)
@@ -1788,7 +1788,19 @@ static enum dc_status enable_link(
        }
 
        if (pipe_ctx->stream_res.audio && status == DC_OK) {
+               struct dc *core_dc = pipe_ctx->stream->ctx->dc;
                /* notify audio driver for audio modes of monitor */
+               struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
+               unsigned int i, num_audio = 1;
+               for (i = 0; i < MAX_PIPES; i++) {
+                       /*current_state not updated yet*/
+                       if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
+                               num_audio++;
+               }
+               if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
+                       /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
+                       pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
+
                pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
 
                /* un-mute audio */
index bbfa83252fc1abd395fc645e5a45fc5a5dc01db8..eac4bfe12257620b2c49625b34b9f85250d76a32 100644 (file)
@@ -91,7 +91,8 @@ struct pp_smu_funcs_rv {
        /* which SMU message?  are reader and writer WM separate SMU msg? */
        void (*set_wm_ranges)(struct pp_smu *pp,
                        struct pp_smu_wm_range_sets *ranges);
-
+       /* PME w/a */
+       void (*set_pme_wa_enable)(struct pp_smu *pp);
 };
 
 #if 0