arm64: dts: imx8mn-evk: enable uart1

Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 2439b91e51d8c79d1d5475b2cbb98b91a8e24695..8fef980c4ab2a38fa6367ff90dc1a5311cd5088a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -247,6 +247,15 @@
        status = "okay";
 };
 
+&uart1 { /* BT */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       assigned-clocks = <&clk IMX8MN_CLK_UART1>;
+       assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
 &uart2 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart2>;
@@ -444,6 +453,15 @@
                >;
        };
 
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
+                       MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
+                       MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
+                       MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
+               >;
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140