arm64: dts: ti: k3-am62a7-sk: Enable ethernet port
authorVignesh Raghavendra <vigneshr@ti.com>
Tue, 3 Jan 2023 04:21:09 +0000 (09:51 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 16 Jan 2023 13:25:12 +0000 (18:55 +0530)
AM62A7 SK has a DP83867 PHY on the board connected to first port of
CPSW, enable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230103042110.1092122-4-vigneshr@ti.com
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts

index 576dbce80ad8363ddd783fcaacbc44ea9e4326c8..bdc363fcbb4b4ad46437168023009412b7143474 100644 (file)
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
 #include "k3-am62a7.dtsi"
 
 / {
                        AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
                >;
        };
+
+       main_mdio1_pins_default: main-mdio1-pins-default {
+               pinctrl-single,pins = <
+                       AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+                       AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+               >;
+       };
+
+       main_rgmii1_pins_default: main-rgmii1-pins-default {
+               pinctrl-single,pins = <
+                       AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+                       AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+                       AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+                       AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+                       AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+                       AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+                       AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+                       AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+                       AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+                       AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+                       AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
+                       AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
+               >;
+       };
 };
 
 &main_i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart0_pins_default>;
 };
+
+&cpsw3g {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+       status = "okay";
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+       status = "disabled";
+};
+
+&cpsw3g_mdio {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mdio1_pins_default>;
+
+       cpsw3g_phy0: ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,min-output-impedance;
+       };
+};