The MIPI divider is also cleared as part of the clock setup sequence, so we
can remove that code.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx6dq
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
         */
 
        if (on) {
-               /*
-                * reset MIPI PCLK/SERCLK divider
-                *
-                * SC PLL CONTRL1 0
-                * - [3..0]:    MIPI PCLK/SERCLK divider
-                */
-               ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, 0x0f, 0);
-               if (ret)
-                       return ret;
-
                /*
                 * configure parallel port control lines polarity
                 *