#define ST_ACCEL_1_DRDY_IRQ_ADDR               0x22
 #define ST_ACCEL_1_DRDY_IRQ_INT1_MASK          0x10
 #define ST_ACCEL_1_DRDY_IRQ_INT2_MASK          0x08
+#define ST_ACCEL_1_IHL_IRQ_ADDR                        0x25
+#define ST_ACCEL_1_IHL_IRQ_MASK                        0x02
 #define ST_ACCEL_1_MULTIREAD_BIT               true
 
 /* CUSTOM VALUES FOR SENSOR 2 */
 #define ST_ACCEL_2_DRDY_IRQ_ADDR               0x22
 #define ST_ACCEL_2_DRDY_IRQ_INT1_MASK          0x02
 #define ST_ACCEL_2_DRDY_IRQ_INT2_MASK          0x10
+#define ST_ACCEL_2_IHL_IRQ_ADDR                        0x22
+#define ST_ACCEL_2_IHL_IRQ_MASK                        0x80
 #define ST_ACCEL_2_MULTIREAD_BIT               true
 
 /* CUSTOM VALUES FOR SENSOR 3 */
 #define ST_ACCEL_3_DRDY_IRQ_ADDR               0x23
 #define ST_ACCEL_3_DRDY_IRQ_INT1_MASK          0x80
 #define ST_ACCEL_3_DRDY_IRQ_INT2_MASK          0x00
+#define ST_ACCEL_3_IHL_IRQ_ADDR                        0x23
+#define ST_ACCEL_3_IHL_IRQ_MASK                        0x40
 #define ST_ACCEL_3_IG1_EN_ADDR                 0x23
 #define ST_ACCEL_3_IG1_EN_MASK                 0x08
 #define ST_ACCEL_3_MULTIREAD_BIT               false
 #define ST_ACCEL_5_DRDY_IRQ_ADDR               0x22
 #define ST_ACCEL_5_DRDY_IRQ_INT1_MASK          0x04
 #define ST_ACCEL_5_DRDY_IRQ_INT2_MASK          0x20
+#define ST_ACCEL_5_IHL_IRQ_ADDR                        0x22
+#define ST_ACCEL_5_IHL_IRQ_MASK                        0x80
 #define ST_ACCEL_5_IG1_EN_ADDR                 0x21
 #define ST_ACCEL_5_IG1_EN_MASK                 0x08
 #define ST_ACCEL_5_MULTIREAD_BIT               false
                        .addr = ST_ACCEL_1_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_ACCEL_1_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_ACCEL_1_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_ACCEL_1_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_ACCEL_1_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_ACCEL_1_MULTIREAD_BIT,
                .bootime = 2,
                        .addr = ST_ACCEL_2_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_ACCEL_2_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_ACCEL_2_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_ACCEL_2_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_ACCEL_2_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_ACCEL_2_MULTIREAD_BIT,
                .bootime = 2,
                        .addr = ST_ACCEL_3_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_ACCEL_3_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_ACCEL_3_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_ACCEL_3_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_ACCEL_3_IHL_IRQ_MASK,
                        .ig1 = {
                                .en_addr = ST_ACCEL_3_IG1_EN_ADDR,
                                .en_mask = ST_ACCEL_3_IG1_EN_MASK,
                        .addr = ST_ACCEL_5_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_ACCEL_5_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_ACCEL_5_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_ACCEL_5_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_ACCEL_5_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_ACCEL_5_MULTIREAD_BIT,
                .bootime = 2, /* guess */
 
 #include <asm/unaligned.h>
 #include <linux/iio/common/st_sensors.h>
 
+#include "st_sensors_core.h"
+
 static inline u32 st_sensors_get_unaligned_le24(const u8 *p)
 {
        return (s32)((p[0] | p[1] << 8 | p[2] << 16) << 8) >> 8;
 }
 
-static int st_sensors_write_data_with_mask(struct iio_dev *indio_dev,
-                                               u8 reg_addr, u8 mask, u8 data)
+int st_sensors_write_data_with_mask(struct iio_dev *indio_dev,
+                                   u8 reg_addr, u8 mask, u8 data)
 {
        int err;
        u8 new_data;
 
--- /dev/null
+/*
+ * Local functions in the ST Sensors core
+ */
+#ifndef __ST_SENSORS_CORE_H
+#define __ST_SENSORS_CORE_H
+int st_sensors_write_data_with_mask(struct iio_dev *indio_dev,
+                                   u8 reg_addr, u8 mask, u8 data);
+#endif
 
 #include <linux/iio/iio.h>
 #include <linux/iio/trigger.h>
 #include <linux/interrupt.h>
-
 #include <linux/iio/common/st_sensors.h>
-
+#include "st_sensors_core.h"
 
 int st_sensors_allocate_trigger(struct iio_dev *indio_dev,
                                const struct iio_trigger_ops *trigger_ops)
 {
-       int err;
+       int err, irq;
        struct st_sensor_data *sdata = iio_priv(indio_dev);
+       unsigned long irq_trig;
 
        sdata->trig = iio_trigger_alloc("%s-trigger", indio_dev->name);
        if (sdata->trig == NULL) {
-               err = -ENOMEM;
                dev_err(&indio_dev->dev, "failed to allocate iio trigger.\n");
-               goto iio_trigger_alloc_error;
+               return -ENOMEM;
        }
 
-       err = request_threaded_irq(sdata->get_irq_data_ready(indio_dev),
+       irq = sdata->get_irq_data_ready(indio_dev);
+       irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
+       /*
+        * If the IRQ is triggered on falling edge, we need to mark the
+        * interrupt as active low, if the hardware supports this.
+        */
+       if (irq_trig == IRQF_TRIGGER_FALLING) {
+               if (!sdata->sensor_settings->drdy_irq.addr_ihl) {
+                       dev_err(&indio_dev->dev,
+                               "falling edge specified for IRQ but hardware "
+                               "only support rising edge, will request "
+                               "rising edge\n");
+                       irq_trig = IRQF_TRIGGER_RISING;
+               } else {
+                       /* Set up INT active low i.e. falling edge */
+                       err = st_sensors_write_data_with_mask(indio_dev,
+                               sdata->sensor_settings->drdy_irq.addr_ihl,
+                               sdata->sensor_settings->drdy_irq.mask_ihl, 1);
+                       if (err < 0)
+                               goto iio_trigger_free;
+                       dev_info(&indio_dev->dev,
+                                "interrupts on the falling edge\n");
+               }
+       } else if (irq_trig == IRQF_TRIGGER_RISING) {
+               dev_info(&indio_dev->dev,
+                        "interrupts on the rising edge\n");
+
+       } else {
+               dev_err(&indio_dev->dev,
+               "unsupported IRQ trigger specified (%lx), only "
+                       "rising and falling edges supported, enforce "
+                       "rising edge\n", irq_trig);
+               irq_trig = IRQF_TRIGGER_RISING;
+       }
+       err = request_threaded_irq(irq,
                        iio_trigger_generic_data_rdy_poll,
                        NULL,
-                       IRQF_TRIGGER_RISING,
+                       irq_trig,
                        sdata->trig->name,
                        sdata->trig);
        if (err) {
                dev_err(&indio_dev->dev, "failed to request trigger IRQ.\n");
-               goto request_irq_error;
+               goto iio_trigger_free;
        }
 
        iio_trigger_set_drvdata(sdata->trig, indio_dev);
 
 iio_trigger_register_error:
        free_irq(sdata->get_irq_data_ready(indio_dev), sdata->trig);
-request_irq_error:
+iio_trigger_free:
        iio_trigger_free(sdata->trig);
-iio_trigger_alloc_error:
        return err;
 }
 EXPORT_SYMBOL(st_sensors_allocate_trigger);
 
                .drdy_irq = {
                        .addr = ST_GYRO_1_DRDY_IRQ_ADDR,
                        .mask_int2 = ST_GYRO_1_DRDY_IRQ_INT2_MASK,
+                       /*
+                        * The sensor has IHL (active low) and open
+                        * drain settings, but only for INT1 and not
+                        * for the DRDY line on INT2.
+                        */
                },
                .multi_read_bit = ST_GYRO_1_MULTIREAD_BIT,
                .bootime = 2,
                .drdy_irq = {
                        .addr = ST_GYRO_2_DRDY_IRQ_ADDR,
                        .mask_int2 = ST_GYRO_2_DRDY_IRQ_INT2_MASK,
+                       /*
+                        * The sensor has IHL (active low) and open
+                        * drain settings, but only for INT1 and not
+                        * for the DRDY line on INT2.
+                        */
                },
                .multi_read_bit = ST_GYRO_2_MULTIREAD_BIT,
                .bootime = 2,
                .drdy_irq = {
                        .addr = ST_GYRO_3_DRDY_IRQ_ADDR,
                        .mask_int2 = ST_GYRO_3_DRDY_IRQ_INT2_MASK,
+                       /*
+                        * The sensor has IHL (active low) and open
+                        * drain settings, but only for INT1 and not
+                        * for the DRDY line on INT2.
+                        */
                },
                .multi_read_bit = ST_GYRO_3_MULTIREAD_BIT,
                .bootime = 2,
 
 #define ST_MAGN_3_BDU_MASK                     0x10
 #define ST_MAGN_3_DRDY_IRQ_ADDR                        0x62
 #define ST_MAGN_3_DRDY_INT_MASK                        0x01
+#define ST_MAGN_3_IHL_IRQ_ADDR                 0x63
+#define ST_MAGN_3_IHL_IRQ_MASK                 0x04
 #define ST_MAGN_3_FS_AVL_15000_GAIN            1500
 #define ST_MAGN_3_MULTIREAD_BIT                        false
 #define ST_MAGN_3_OUT_X_L_ADDR                 0x68
                .drdy_irq = {
                        .addr = ST_MAGN_3_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_MAGN_3_DRDY_INT_MASK,
+                       .addr_ihl = ST_MAGN_3_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_MAGN_3_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_MAGN_3_MULTIREAD_BIT,
                .bootime = 2,
 
 #define ST_PRESS_LPS331AP_DRDY_IRQ_ADDR                0x22
 #define ST_PRESS_LPS331AP_DRDY_IRQ_INT1_MASK   0x04
 #define ST_PRESS_LPS331AP_DRDY_IRQ_INT2_MASK   0x20
+#define ST_PRESS_LPS331AP_IHL_IRQ_ADDR         0x22
+#define ST_PRESS_LPS331AP_IHL_IRQ_MASK         0x80
 #define ST_PRESS_LPS331AP_MULTIREAD_BIT                true
 #define ST_PRESS_LPS331AP_TEMP_OFFSET          42500
 
 #define ST_PRESS_LPS25H_DRDY_IRQ_ADDR          0x23
 #define ST_PRESS_LPS25H_DRDY_IRQ_INT1_MASK     0x01
 #define ST_PRESS_LPS25H_DRDY_IRQ_INT2_MASK     0x10
+#define ST_PRESS_LPS25H_IHL_IRQ_ADDR           0x22
+#define ST_PRESS_LPS25H_IHL_IRQ_MASK           0x80
 #define ST_PRESS_LPS25H_MULTIREAD_BIT          true
 #define ST_PRESS_LPS25H_TEMP_OFFSET            42500
 #define ST_PRESS_LPS25H_OUT_XL_ADDR            0x28
                        .addr = ST_PRESS_LPS331AP_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_PRESS_LPS331AP_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_PRESS_LPS331AP_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_PRESS_LPS331AP_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_PRESS_LPS331AP_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_PRESS_LPS331AP_MULTIREAD_BIT,
                .bootime = 2,
                        .addr = ST_PRESS_LPS25H_DRDY_IRQ_ADDR,
                        .mask_int1 = ST_PRESS_LPS25H_DRDY_IRQ_INT1_MASK,
                        .mask_int2 = ST_PRESS_LPS25H_DRDY_IRQ_INT2_MASK,
+                       .addr_ihl = ST_PRESS_LPS25H_IHL_IRQ_ADDR,
+                       .mask_ihl = ST_PRESS_LPS25H_IHL_IRQ_MASK,
                },
                .multi_read_bit = ST_PRESS_LPS25H_MULTIREAD_BIT,
                .bootime = 2,
 
  * @addr: address of the register.
  * @mask_int1: mask to enable/disable IRQ on INT1 pin.
  * @mask_int2: mask to enable/disable IRQ on INT2 pin.
+ * @addr_ihl: address to enable/disable active low on the INT lines.
+ * @mask_ihl: mask to enable/disable active low on the INT lines.
  * struct ig1 - represents the Interrupt Generator 1 of sensors.
  * @en_addr: address of the enable ig1 register.
  * @en_mask: mask to write the on/off value for enable.
        u8 addr;
        u8 mask_int1;
        u8 mask_int2;
+       u8 addr_ihl;
+       u8 mask_ihl;
        struct {
                u8 en_addr;
                u8 en_mask;