arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node

Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).

Move the MDIO pins pinmux to the MIDO nodes.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-8-afd@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 2dec25d9024071b2c8926275d075eea3f5eb1dc7..2319ba4f5ae33e4fa9249cba8e6b0a3c182608cf 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -425,8 +425,7 @@
 
 &cpsw3g {
        pinctrl-names = "default";
-       pinctrl-0 = <&mdio1_pins_default
-                    &rgmii1_pins_default
+       pinctrl-0 = <&rgmii1_pins_default
                     &rgmii2_pins_default>;
 };
 
@@ -441,6 +440,9 @@
 };
 
 &cpsw3g_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mdio1_pins_default>;
+
        cpsw3g_phy0: ethernet-phy@0 {
                reg = <0>;
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 58c71608d925b78dbc88d670c2c2cade354e8c50..c1d634647027269b46167c940b2da512d4a8fb6c 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -439,8 +439,7 @@
 
 &cpsw3g {
        pinctrl-names = "default";
-       pinctrl-0 = <&mdio1_pins_default
-                    &rgmii1_pins_default
+       pinctrl-0 = <&rgmii1_pins_default
                     &rgmii2_pins_default>;
 };
 
@@ -455,6 +454,9 @@
 };
 
 &cpsw3g_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mdio1_pins_default>;
+
        cpsw3g_phy0: ethernet-phy@0 {
                reg = <0>;
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;