ASoC: SOC: Intel: introduce cl_init callback
authorBard Liao <yung-chuan.liao@linux.intel.com>
Wed, 15 Jun 2022 08:43:47 +0000 (16:43 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 15 Jun 2022 08:56:56 +0000 (09:56 +0100)
The code loader init sequences are different between versions of
Intel platforms. Have a cl_init callback allows us to reuse the
common code.
No function changed.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220615084348.3489-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda-loader.c
sound/soc/sof/intel/hda.h
sound/soc/sof/intel/icl.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index 0cea280a6d2d3129334ecbf312bc60f80c09d0b8..084c245a952288a66cc3ef3e8c7fb874de9adeeb 100644 (file)
@@ -101,6 +101,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .ssp_base_offset = APL_SSP_BASE_OFFSET,
        .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
 };
 EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index cd6e5f8a5eb4dfdad775c4f34d313ef3c7d32220..ccf46fcd6c9abf35843c789c52a694dd208c7452 100644 (file)
@@ -401,6 +401,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_1_8,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -430,6 +431,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index d3ec5996a9a3d1fa092b01d1bdc1be2a5ceb6fd1..9e99f376f2b33da3e3d3c9f4a6545a52d8be04eb 100644 (file)
@@ -99,7 +99,7 @@ out_put:
  * power on all host managed cores and only unstall/run the boot core to boot the
  * DSP then turn off all non boot cores (if any) is powered on.
  */
-static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
+int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
 {
        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
        const struct sof_intel_dsp_desc *chip = hda->desc;
@@ -369,9 +369,15 @@ int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
 
 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
 {
+       const struct sof_intel_dsp_desc *chip_info;
        int ret;
 
-       ret = cl_dsp_init(sdev, 0, true);
+       chip_info = get_chip_info(sdev->pdata);
+       if (chip_info->cl_init)
+               ret = chip_info->cl_init(sdev, 0, true);
+       else
+               ret = -EINVAL;
+
        if (!ret)
                hda_sdw_process_wakeen(sdev);
 
@@ -430,7 +436,10 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
                        "Attempting iteration %d of Core En/ROM load...\n", i);
 
                hda->boot_iteration = i + 1;
-               ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag, false);
+               if (chip_info->cl_init)
+                       ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
+               else
+                       ret = -EINVAL;
 
                /* don't retry anymore if successful */
                if (!ret)
index f4e4cd7d7406785cfd282976c6f2d20aa2fdaec2..8b7f3c07d4785a562da94086ac1e9beede52a51a 100644 (file)
@@ -602,6 +602,7 @@ struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned
                                              int direction);
 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
                   struct hdac_ext_stream *hext_stream);
+int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 #define HDA_CL_STREAM_FORMAT 0x40
 
 /* pre and post fw run ops */
index f19517dffd62426a42958e2069f2728a90b80b50..4e37b7fe06274db5356be18e5056a5170eba82ca 100644 (file)
@@ -152,6 +152,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 1fd7b485d8212efb190a95a42e24298d2fc0902c..371991fa474f0d420c42b5c182d3d2c561d2446c 100644 (file)
@@ -185,6 +185,7 @@ struct sof_intel_dsp_desc {
        enum sof_intel_hw_ip_version hw_ip_version;
        bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
        bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
+       int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 };
 
 extern struct snd_sof_dsp_ops sof_tng_ops;
index dcad7c382de69df9edae92add483fef98de43df2..6dfb4786c7824620556aa564b6f9243e5e0fb034 100644 (file)
@@ -127,6 +127,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -149,6 +150,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -171,6 +173,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -193,6 +196,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);