Armada 3700 SPI controller has an internal clock divider which can
divide the parent clock frequency by up to 30.
This patch sets the limits in the spi_controller fields so that we can
detect when a non-supported frequency is requested by a device for a
transfer.
Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr>
Signed-off-by: Mark Brown <broonie@kernel.org>
 
 #define DRIVER_NAME                    "armada_3700_spi"
 
+#define A3700_SPI_MAX_SPEED_HZ         100000000
+#define A3700_SPI_MAX_PRESCALE         30
 #define A3700_SPI_TIMEOUT              10
 
 /* SPI Register Offest */
                goto error;
        }
 
+       master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
+                                       clk_get_rate(spi->clk));
+       master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
+                                               A3700_SPI_MAX_PRESCALE);
+
        ret = a3700_spi_init(spi);
        if (ret)
                goto error_clk;