if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
                cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
 
+       dev_dbg(icd->parent, "vsync active %s, hsync active %s, sampling on pix clock %s edge\n",
+               common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? "low" : "high",
+               common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? "low" : "high",
+               common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING ? "falling" : "rising");
+
        if (isi->pdata.has_emb_sync)
                cfg1 |= ISI_CFG1_EMB_SYNC;
        if (isi->pdata.full_mode)
                return -EINVAL;
        }
 
+       if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+               isi->pdata.hsync_act_low = true;
+       if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+               isi->pdata.vsync_act_low = true;
+       if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
+               isi->pdata.pclk_act_falling = true;
+
+       if (ep.bus_type == V4L2_MBUS_BT656)
+               isi->pdata.has_emb_sync = true;
+
        return 0;
 }