riscv: dts: starfive: jh7110: add dma controller node

Add the dma controller node for the Starfive JH7110 SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ecd4160b2f5425a5b6ddf927a0f9e47507520de9..1a65f6848560d258338790fa8ba2ee5d5919fe78 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -843,6 +843,24 @@
                        status = "disabled";
                };
 
+               dma: dma-controller@16050000 {
+                       compatible = "starfive,jh7110-axi-dma";
+                       reg = <0x0 0x16050000 0x0 0x10000>;
+                       clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+                                <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+                       clock-names = "core-clk", "cfgr-clk";
+                       resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+                                <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+                       interrupts = <73>;
+                       #dma-cells = <1>;
+                       dma-channels = <4>;
+                       snps,dma-masters = <1>;
+                       snps,data-width = <3>;
+                       snps,block-size = <65536 65536 65536 65536>;
+                       snps,priority = <0 1 2 3>;
+                       snps,axi-max-burst-len = <16>;
+               };
+
                aoncrg: clock-controller@17000000 {
                        compatible = "starfive,jh7110-aoncrg";
                        reg = <0x0 0x17000000 0x0 0x10000>;